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gpa

GPU Performance Advisor

hbm

High Bandwidth Memory (HBM) timing model based on DRAMSim2

hdmi

Send video/audio over HDMI on an FPGA

hexl-fpga

Intel Homomorphic Encryption Acceleration Library for FPGAs, including open source implementation of FPGA kernels for accelerating NTT, INTT, and Dyadic Multiplication modular arithmetic operations, FPGA runtime, and APIs for connecting to third-party homomorphic encryption libraries.

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

improving_per_esti_for_fpga-based_acc_for_cnns-arc2020

A codebase accompanying the paper "Improving Performance Estimation for FPGA-based Accelerators for Convolutional Neural Networks", by Ferianc et al. presented at ARC'2020

inter-operator-scheduler

IOS: Inter-Operator Scheduler for CNN Acceleration

interstellar-cnn-scheduler

Tool for optimize CNN blocking

iob-cache

Verilog configurable cache

iob-mem

Verilog behavioral description of various memories

iob-versat

Coarse Grained Reconfigurable Array

itri-opendla

Express DLA implementation for FPGA, revised based on NVDLA.

jetson_benchmarks

Jetson Benchmark

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

lee-slam-source

SLAM 开发学习资源与经验分享

leflow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

lenet_accelerator

A Lenet ASIC Design targeting minimum number of cycles

linefs

LineFS: Efficient SmartNIC Offload of a Distributed File System with Pipeline Parallelism

litepcie

Small footprint and configurable PCIe core

llmsys-paperlist

LLM Systems Paper List

maeri

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

maestro

A dev version of MAESTRO

maestro-stable

An analytical cost model of DNN Dataflows (http://synergy.ece.gatech.edu/tools/maestro/)

magicube

Magicube is a high-performance library for quantized sparse matrix operations (SpMM and SDDMM) of deep learning on Tensor Cores.

matrix-multiplication

Design for 4 x 4 Matrix Multiplication using Verilog

mcpat

An integrated power, area, and timing modeling framework for multicore and manycore architectures

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

microsoft-activation-scripts

A Windows and Office activator using HWID / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.

microswitch-noc