wxbbuaa2011 Goto Github PK

awesome-tensor-compilers

A list of awesome compiler projects and papers for tensor computation and deep learning.

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

backdoor-learning-resources

A curated list of backdoor learning resources

bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

booksim2

BookSim 2.0

brian2

Brian is a free, open source simulator for spiking neural networks.

buffets

Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

butterfly_acc

The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

bwlock

dynamic memory bandwidth management framework

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

chisel-book

Hardware design with Chisel

chisel-examples

Chisel examples and code snippets

chisel-sift

chronos

The Chronos FPGA Framework to accelerate ordered applications

cmnnc

Computational Memory Neural Network Compiler

cnn-accelerator-vlsi

Convolutional accelerator kernel, target ASIC & FPGA

cnn-benchmarks

Benchmarks for popular CNN models

cnn-gpu-benchmarks

Latest (2020) CNN and GPU Benchmarks on ImageNet and CIFAR

cnn-workload

Benchmarks the computational/memory workload of popular CNN models

cnnergy

An Analytical CNN Energy Model

cnnhwpe

cocopie-modelzoo

concurrentqueue

A fast multi-producer, multi-consumer lock-free concurrent queue for C++11

conference-acceptance-rate-for-computer-architecture

constellation

A Chisel RTL generator for network-on-chip interconnects

convnet-burden

Memory consumption and FLOP count estimates for convnets

convolution_kernel

Accelerating CNN's convolution operation on GPUs by using memory-efficient data access patterns.

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

corundum

Open source, high performance, FPGA-based NIC

cosa

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)