SC126 Custom Build - Wrong serial baudrate when changing Z180_CLKDIV about romwbw

[wwarthen]

Hi Jose,

Sounds like you have mastered the process of building a custom ROM. Excellent.

The problem you are encountering is that the Z180 ASCI serial ports have a limited set of baud rate divisors. When the CPU clock rate is set to 9.216 MHz (as you have done), there is no baud rate divisor in the Z180 that will result in 38,400 baud. RomWBW has a failsafe mechanism when it is unable to find a suitable divisor for the requested baud rate. This failsafe ensures that the serial will still work, but it just finds an arbitrary baudrate that works.

In the Doc directory of RomWBW, look at the file called "Z180 ASCI Baud Rate Options.pdf". If you look at the column for 9.216 MHz CPU Clock Rate, you will see the baud rates that are possible for that clock rate.

Good luck!

Wayne

[MorfeoMatrixx]

Many thanks Wayne for your zero-wait-state response ;-)
I'll try a valid baud rate for the half speed clock tonight and let you know any problem.
Cheers, JL.

[wwarthen]

Hope it goes well -- it should. I need to find a way to put this Z180 baud rate restriction in the documentation somewhere that is more obvious!

…

On Thu, Nov 14, 2019 at 11:12 AM MorfeoMatrixx ***@***.***> wrote: Many thanks Wayne for your zero-wait-state response ;-) I'll try a valid baud rate for the half speed clock tonight and let you know any problem. Cheers, JL. — You are receiving this because you modified the open/close state. Reply to this email directly, view it on GitHub <#56?email_source=notifications&email_token=AATNT2P336SVASUCG27W7LLQTWPLRA5CNFSM4JNEAEDKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEEC6U7A#issuecomment-554035836>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AATNT2J33NAYCDAMMSMVD7DQTWPLRANCNFSM4JNEAEDA> .

[MorfeoMatrixx]

Worked perfectly at 57,600 bps !
I also changed the LEDENABLE value to TRUE to activate Steve's patch for the Diag LEDs and now they turn off after booting CP/M and show drive activity. Neat; I sugest setting this as the default behavior for SC126 & SC130 boards.

Cheers, JL.

[wwarthen]

Hmmm... I thought it was the default. I will check on this. Thanks.

[wwarthen]

I just checked and it sure looks to me like LEDENABLE's default value is TRUE. It is set in the base config file "cfg_scz180.asm". The base value for LEDENABLE is not overridden in either "SCZ180_126.asm" or "SCZ180_130.asm", so it should be TRUE in the default build configuration for both boards.

Let me know if you think I am missing something.

Thanks,

Wayne

[MorfeoMatrixx]

The problem is that I'm still using the stock ROM, that predates the change...

---

RetroBrew HBIOS v2.9.2-pre.1, 2019-07-23

RC2014 Z8S180-N @ 18.428MHz IO=0xC0
0 MEM W/S, 2 I/O W/S, INT MODE 2
512KB ROM, 512KB RAM

---

By the way, running the provided FLASH4 program to update my ROM, returned the message below. I sent Will an email so he can add support for your SST39SF040 chips.

---

CP/M-80 v2.2, 54.0K TPA

B>dir flash*.*
B: FLASH COM
B>flash read romwbw00.bin
FLASH4 by Will Sowerbutts [email protected] version 1.2.3

Using RomWBW (v2.6+) bank switching.
Flash memory chip ID is 0xC340: Unknown flash chip.
Your flash memory chip is not recognised.
Please email [email protected] if you would like support for your
system added to this program.

B>

---

Cheers, JL.

[b1ackmai1er]

Hi, No problem reading or writing SST39F040 on my SBC V2 (10Mhz)

…

-------------------- flash read and write existing rom image RetroBrew HBIOS v2.9.2-pre.18, 2019-10-20 SBC Z80 @ 9.556MHz 0 MEM W/S, 1 I/O W/S, INT MODE 2 512KB ROM, 512KB RAM G>flash read text.rom FLASH4 by Will Sowerbutts <[email protected]> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Read complete. G>flash write text.rom FLASH4 by Will Sowerbutts <[email protected]> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Write complete: Reprogrammed 0/128 sectors.

------- flash new image G>flash write zpp.rom FLASH4 by Will Sowerbutts <[email protected]> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Write complete: Reprogrammed 0/128 sectors. RetroBrew HBIOS v2.9.2-pre.21, 2019-11-16 SBC Z80 @ 9.924MHz 0 MEM W/S, 1 I/O W/S, INT MODE 2 512KB ROM, 512KB RAM---

---- Quite a comprehensive list of flash chip id's here : https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/master/flashchips.h which do not include *0xC340*? Id's in this list for the 39F40/39SF040 match the data sheet: SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39SF040 Device ID = B7H, is read with A0 = 1 Regards Phil.

On Sat, Nov 16, 2019 at 7:07 AM MorfeoMatrixx ***@***.***> wrote: The problem is that I'm still using the stock ROM, that predates the change... ------------------------------ *RetroBrew HBIOS v2.9.2-pre.1, 2019-07-23* RC2014 Z8S180-N @ 18.428MHz IO=0xC0 0 MEM W/S, 2 I/O W/S, INT MODE 2 512KB ROM, 512KB RAM ------------------------------ By the way, running the provided FLASH4 program to update my ROM, returned the message below. I sent Will an email so he can add support for your *SST39SF040* chips. ------------------------------ CP/M-80 v2.2, 54.0K TPA B>dir flash*.* B: FLASH COM B>flash read romwbw00.bin FLASH4 by Will Sowerbutts ***@***.*** version 1.2.3 Using RomWBW (v2.6+) bank switching. *Flash memory chip ID is 0xC340: Unknown flash chip. Your flash memory chip is not recognised.* Please email ***@***.*** if you would like support for your system added to this program. B> ------------------------------ Cheers, JL. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#56?email_source=notifications&email_token=AJM7HV4QIJNEZLO2OYI5TFTQT4TR7A5CNFSM4JNEAEDKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEEG7THA#issuecomment-554563996>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AJM7HVYLP3JW5R2USUAJZPLQT4TR7ANCNFSM4JNEAEDA> .

[MorfeoMatrixx]

Hi All, now working OK with my SC126 using an AM29F040B chip (I didn't want to overwrite my stock chip and potentially brick my board) *A>flash write j:romjlc.rom* *FLASH4 by Will Sowerbutts <[email protected] <[email protected]>> version 1.2.3* *Using RomWBW (v2.6+) bank switching.* *Flash memory chip ID is 0x01A4: 29F040* *Flash memory has 8 sectors of 65536 bytes, total 512KB* *Write complete: Reprogrammed 6/8 sectors.* *Verify (8 sectors) complete: OK!* *A>* The program, in order to correctly read the chip-id, *eihter reading or writing*, needs the Write-Protect jumper (JP1 or JP2) set to the Write/Enable position, so /WE is connected to the CPU /WR signal. @will: this is the confirmation you were looking for. The SC126 with the current pre.20 firmware, albeit been a dual ROM board, handles a single chip at a time, selected with the JP3 jumper. The software controlled bank selection for the ROM is not implemented at the moment (perhaps Wayne, the designer of the board, can give you more details on this, he's the Yoda Master, I'm a humble user). Regards, José Luis. On Sat, Nov 16, 2019 at 6:33 AM b1ackmai1er <[email protected]> wrote:

…

Hi, No problem reading or writing SST39F040 on my SBC V2 (10Mhz) -------------------- flash read and write existing rom image RetroBrew HBIOS v2.9.2-pre.18, 2019-10-20 SBC Z80 @ 9.556MHz 0 MEM W/S, 1 I/O W/S, INT MODE 2 512KB ROM, 512KB RAM G>flash read text.rom FLASH4 by Will Sowerbutts ***@***.***> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Read complete. G>flash write text.rom FLASH4 by Will Sowerbutts ***@***.***> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Write complete: Reprogrammed 0/128 sectors. ------- flash new image G>flash write zpp.rom FLASH4 by Will Sowerbutts ***@***.***> version 1.2.3 Using RomWBW (v2.6+) bank switching. Flash memory chip ID is 0xBFB7: 39F040 Flash memory has 128 sectors of 4096 bytes, total 512KB Write complete: Reprogrammed 0/128 sectors. RetroBrew HBIOS v2.9.2-pre.21, 2019-11-16 SBC Z80 @ 9.924MHz 0 MEM W/S, 1 I/O W/S, INT MODE 2 512KB ROM, 512KB RAM--- ---- Quite a comprehensive list of flash chip id's here : https://chromium.googlesource.com/chromiumos/third_party/flashrom/+/master/flashchips.h which do not include *0xC340*? Id's in this list for the 39F40/39SF040 match the data sheet: SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39SF040 Device ID = B7H, is read with A0 = 1 Regards Phil. On Sat, Nov 16, 2019 at 7:07 AM MorfeoMatrixx ***@***.***> wrote: > The problem is that I'm still using the stock ROM, that predates the > change... > ------------------------------ > > *RetroBrew HBIOS v2.9.2-pre.1, 2019-07-23* > > RC2014 Z8S180-N @ 18.428MHz IO=0xC0 > 0 MEM W/S, 2 I/O W/S, INT MODE 2 > 512KB ROM, 512KB RAM > ------------------------------ > > By the way, running the provided FLASH4 program to update my ROM, returned > the message below. I sent Will an email so he can add support for your > *SST39SF040* chips. > ------------------------------ > > CP/M-80 v2.2, 54.0K TPA > > B>dir flash*.* > B: FLASH COM > B>flash read romwbw00.bin > FLASH4 by Will Sowerbutts ***@***.*** version 1.2.3 > > Using RomWBW (v2.6+) bank switching. > > *Flash memory chip ID is 0xC340: Unknown flash chip. Your flash memory > chip is not recognised.* > Please email ***@***.*** if you would like support for your > system added to this program. > > B> > ------------------------------ > > Cheers, JL. > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > < #56?email_source=notifications&email_token=AJM7HV4QIJNEZLO2OYI5TFTQT4TR7A5CNFSM4JNEAEDKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEEG7THA#issuecomment-554563996 >, > or unsubscribe > < https://github.com/notifications/unsubscribe-auth/AJM7HVYLP3JW5R2USUAJZPLQT4TR7ANCNFSM4JNEAEDA > > . > — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#56?email_source=notifications&email_token=ACCWCKDJ54ZI4U7NA5ZWSYDQT646HA5CNFSM4JNEAEDKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEEHNQOA#issuecomment-554620984>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACCWCKCA2C2M7WVUXMVBDYDQT646HANCNFSM4JNEAEDA> .

[wwarthen]

The software controlled bank selection for the ROM is not
implemented at the moment (perhaps Wayne, the designer of the board, can
give you more details on this, he's the Yoda Master, I'm a humble user).

Just want to clarify that the designer (and producer) of the SC126 board is actually Steve Cousins.

Thanks,

Wayne

[will]

@will: this is the confirmation you were looking for.

i'm not looking for any sort of confirmation, wtf

[wwarthen]

@will: this is the confirmation you were looking for.

i'm not looking for any sort of confirmation, wtf

I think @MorfeoMatrixx intended the comment for Will Sowerbutts. Wrong Will.

-Wayne