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weichi-zhang's Projects

ara icon ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

fictiondown icon fictiondown

小说下载|小说爬取|起点|笔趣阁|导出Markdown|导出txt|转换epub|广告过滤|自动校对

fp_fma icon fp_fma

ISSCS PICO 2021 Contest Submission

fpu icon fpu

集成Berkeley hardfloat的,可以直接用于RISC-V处理器单精度FPU实现的小模块

git icon git

A fork of Git containing Windows-specific patches.

pythia-hdl icon pythia-hdl

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL.

quasar icon quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

ramulator icon ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

xiangshan icon xiangshan

Open-source high-performance RISC-V processor

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