weichi-zhang Goto Github PK

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

berkeley-hardfloat

biriscv

32-bit Superscalar RISC-V CPU

block-inclusivecache-sifive

chipsalliance-playground

chipyard in mill :P

drawio-desktop

Official electron build of draw.io

e203_hbirdv2

The Ultra-Low Power RISC-V Core

fictiondown

小说下载|小说爬取|起点|笔趣阁|导出Markdown|导出txt|转换epub|广告过滤|自动校对

fp_fma

ISSCS PICO 2021 Contest Submission

fpu

集成Berkeley hardfloat的，可以直接用于RISC-V处理器单精度FPU实现的小模块

git

A fork of Git containing Windows-specific patches.

openc910

OpenXuantie - OpenC910 Core

pythia-hdl

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL.

quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-isa-manual

RISC-V Instruction Set Manual

rocket-chip

Rocket Chip Generator

sparc64soc

OpenSPARC-based SoC

typroaction

A Github Action about Ty (Pro Version)

xiangshan

Open-source high-performance RISC-V processor