vignesh-raghavan Goto Github PK

aes128

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

crc32

32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.

gpu

ECE 695 Course at Purdue (CUDA)

parallel-programming

ECE 563 Course at PURDUE.

sat

sat-solver

The SAT solver checks if the given CNF formula evaluates to true for some arbitrary input combinations.