vhdlf Goto Github PK
Type: Organization
Bio: A summary of VHDL examples and projects.
Blog: https://vhdlf.github.io/
vhdlf's Projects
blink
Blinks an LED.
button
Blinks LED when button is pressed.
cpu_basic
Design of a pentium-like 32-bit CPU.
first_component
Creating first component and using multiple processes.
gardintrapp--cpu_4004
4-bit CPU
gate_and
The AND gate is a basic digital logic gate that implements logical conjunction.
gate_imply
The IMPLY gate is a digital logic gate that implements a logical conditional.
gate_nand
The NAND gate (NOT-AND) is a logic gate that outputs false only if all its inputs are true.
gate_nor
The NOR gate (NOT-OR) is a logic gate that outputs true only if all its inputs are false.
gate_not
The NOT gate is a logic gate which implements logical negation.
gate_or
The OR gate is a basic digital logic gate that implements logical disjunction.
gate_xnor
The XNOR gate (Exclusive NOR) is a logic gate that outputs true only if even number of inputs are true.
gate_xor
The XOR gate (Exclusive OR) is a logic gate that outputs true only if odd number of inputs are true.
multiple_components
Create multiple components.
texane--vhdl
VHDL related contents.
vhdlf.github.io
A summary of VHDL examples and projects.
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