Comments (2)
Adding @duck2 as the likely driver of this.
from vtr-verilog-to-routing.
@duck2 It seems the newer version is breaking a few things: https://github.com/verilog-to-routing/vtr-verilog-to-routing/actions/runs/6829459730/job/18575644801?pr=2437#step:5:2005.
I'm going to try and fix them on my PR today.
from vtr-verilog-to-routing.
Related Issues (20)
- VPR warning verbosity with timing analysis on and custom routing graphs with isolated clock routing
- VTR format checking / auto-format not checked by CI?
- Make a short coding style guide in the VTR developer guide
- vtr optional documentation showing up at the top of vtr::vector and vtr::vector_map documentation HOT 2
- redundant adders when synthesizing addition with full adders HOT 2
- Placement Constraints not working HOT 8
- [Logging] Incorrect LUT Sizes Circuit Statistic Printing
- [Logging] Overly Verbose Log Messages When Building RRGraph HOT 3
- [Netlist] Potential Issue When Re-Creating Elements in Atom and Clustered Netlists HOT 2
- if VPR have routing constraint like Xilinx fixed routing
- 3D switch block updates & commenting
- ./kernel/yosys.h:42:10: fatal error: 'map' file not found HOT 3
- [IPA] MVP to manually test vpr --server mode HOT 3
- [Build] VTR Fails to Build on ASSERT_LEVEL=4 HOT 2
- Issue with Multibit Adder in VTR flagship architecture
- VTR throws warning for shorted SB connections
- (Caused by io location changed)The suspicious detour phenomenon that significantly reduces the slack
- Multibit Adder Architecture Failure
- VTR seems to struggle with being smart about how it packs into memories
- Improve 3D switch block commenting and move command line option to arch file
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