ved-rivos Goto Github PK
Name: Ved Shanbhogue
Type: User
Company: Rivos Inc.
Bio: https://www.linkedin.com/in/vedvyas-shanbhogue-b4a3622/
Location: Austin, TX
Name: Ved Shanbhogue
Type: User
Company: Rivos Inc.
Bio: https://www.linkedin.com/in/vedvyas-shanbhogue-b4a3622/
Location: Austin, TX
RISC-V IOMMU in verilog
Linux kernel source tree
OpenTitan: Open source silicon root of trust
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
"B" extension - that represents the collection of the Zba, Zbb, Zbs extensions
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
RISC-V Configuration Validator
RISC-V cryptography extensions standardisation work.
Working Draft of the RISC-V Debug Specification Standard
RISC-V Double Trap Fast-Track Extension
The repo will be used to hold the draft non-ISA IOMMU specification under codevelopment by the IOMMU TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
RISC-V Instruction Set Manual
Spike, a RISC-V ISA Simulator
RISC-V Opcodes
RISC-V Profiles and Platform Specification
RISC-V Architecture Profiles
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configur
RISC-V Security Model
RISC-V Server Plaftorm
This specification will define the Smmtt privilege ISA extensions required to support the supervisor domain isolation for many isolation use cases e.g. confidential-computing, fault isolation and so on.
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
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