Comments (10)
Hi,
Have you downloaded the FTD3XX.dll file from FTDI http://www.ftdichip.com/Drivers/D3XX.htm and placed it in the same folder as the pcileech.exe binary? Also please make sure it's the x64-version of the dll you place alongside pcileech.exe
from pcileech-fpga.
Yes, i have done this. when i run the pcileech.exe probe command it hangs for a second before returning with the error message.
from pcileech-fpga.
The FTDI also needs to show up cleanly in Windows Device Manager, and the SP605 have to be connected to PCIe on the target at the time when running the probe or any other command.
How are the status LEDs looking on the SP605? DS3, DS4 should not be lit, while DS5 should be lit if you have a correct PCIe link.
from pcileech-fpga.
Thank you for your fast reply again.
I have checked both device manager and the LED's
I believe they are correct. Attached are photos of both.
from pcileech-fpga.
oh its working now. thanks for your help. just needed a device reboot i think
from pcileech-fpga.
awsome 👍 and thanks for letting me know.
sometimes it also helps to press the reset button on the SP605 board and the reset button on the FT601 board. reboot is also sometimes required, it seems to be dependant on the target system.
Please let me know if you have any improvements suggestions for the FPGA stuff, I'm currently working on a faster better bitstream, but other than that :)
from pcileech-fpga.
excellent. This is a good project. it does seem very intermittent. works when pc is rebooted and adapter is connected though. Speeds when dumping ram seem to be low due to a large amount of Bad TLP received. maybe its just my machine though.
from pcileech-fpga.
Thanks,
About the bad TLPs, it's a known bug which I thought I had "resolved" by setting an extra delay in pcileech.exe; It's working on my test hardware. A workaround might be if you set in device605_601.c
the lines with usleep(300);
to usleep(500);
and recompile. Or running pcileech.exe with the option -iosize 0x4000
might also help.
Hopefully these issues will be resolved completely once I release the new bitstream which should resolve these bugs. That is a couple of weeks away though.
from pcileech-fpga.
yeah thats done the trick. speeds back to 70mbs with no bad TLP. i am struggling to get this to work while hotplugging via pcie. still only will connect when booted with spartan 6 plugged in.
from pcileech-fpga.
Awesome that you got it to work. As previously stated I hope the new bitstream that is planned will resolve these issues.
About hotplug - it's highly dependent on the target system if it will work or not. It's not much I can do about it unfortunately. On some systems it works, on others it doesn't :/
from pcileech-fpga.
Related Issues (20)
- Flash memory can be programmed but not used. What should I do to fix it? HOT 1
- about memory issue HOT 3
- Does the firmware support Kintex 7 Chips? HOT 1
- Q about TLP completion timeout HOT 1
- Xilinx PCIe parameters HOT 3
- Q on receiving data from FPGA HOT 3
- Question: Can I effectively use the Screamer PCIe Squirrel in a single PC setup. HOT 1
- 0x55556666 padding in the middle of receiving a TLP? HOT 4
- This device cannot be started. (Code 10) HOT 1
- pls help me HOT 2
- About solutions to some problems and some overlooked code. HOT 20
- Advice Request: Ported project to new board and 1Gbit Ethernet, how can I make it faster? HOT 5
- Is it possible to limit the number and frequency of TLPs that are actively sent on the software side?
- Keys HOT 1
- memory issue HOT 1
- Leetdma Abnormal speed measurement
- Leetdma Abnormal speed measurement HOT 2
- How to fix disconnect to the fpga board HOT 1
- ERROR: [Common 17-170] Error when generating project files HOT 6
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