[Branch new-devices] Icenet not publically accessible about fpga-zynq

[davidbiancolin]

I think this was discussed in the RV mailing list but my suggestion is to look here at the SiFive freedom platform. They both provide shims for RocketChip-based FPGA prototypes, and provide an SDK with a consistent snapshots of the toolchain, linux, and glibc.
See https://github.com/sifive/freedom.

As you point out, this repository is stale. We're are considering deprecating it by the end of the year, as there are now other better maintained FPGA-prototypes of RocketChip, not to mention other RISC-V implementations intended for FPGAs.

Here at Berkeley we're working on a bunch of FPGA-accelerated infrastructure (see MIDAS: https://github.com/ucb-bar/midas-release), but if you're looking for simply direct implementation of RocketChip RTL on an FPGA (an FPGA prototype), the SiFive freedom platform is a better starting point.

[davidbiancolin]

Master has been updated with IceNet removed.