Comments (9)
davidbiancolin
commented on May 18, 2024
Do you know why the parent process died?
from fpga-zynq.
ninode
commented on May 18, 2024
Because of the make bitstream command (make_bitstream_ZynqConfig.tcl).
Make rocket and make project succeeded. And this happens right after the area optimization.
Also after the synthesis begins, this shows:
source src/tcl/make_bitstream_ZynqConfig.tcl
# open_project zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/alpha/Xilinx/Vivado/2016.2/data/ip'.
# reset_run synth_1
# reset_run impl_1
# launch_runs synth_1
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
# launch_runs synth_1
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
Is this relevant or problematic ?
Here's more of log:
Report RTL Partitions:
+------+------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+------------------------+------------+----------+
|1 |FPU__GB0 | 1| 27150|
|2 |FPU__GB1 | 1| 22422|
|3 |RocketTile__GCB0 | 1| 17734|
|4 |HellaCache | 1| 9703|
|5 |RocketTile__GCB2 | 1| 11300|
|6 |L2BroadcastHub | 1| 29520|
|7 |DefaultCoreplex__GCB1 | 1| 3335|
|8 |FPGAZynqTop__GC0 | 1| 8331|
|9 |ZynqAXISlave | 1| 491|
|10 |rocketchip_wrapper__GC0 | 1| 1741|
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:51 ; elapsed = 00:10:51 . Memory (MB): peak = 2724.598 ; gain = 1841.562 ; free physical = 80 ; free virtual = 264
I could provide all the log content if you want.
from fpga-zynq.
ninode
commented on May 18, 2024
Also I don't know if it was because I did it wrong. So here's what I did.
-I have Vivado 2016.2 and its settings64.sh and a JVM that runs scala
-make init-submodules yileds no rule to make target
-in testchipip: git submodule update --init
-in rocket-chip! git submodule update --init
-in rocket-chip/riscv-tools: git submodule update --init --recursive and ./build.sh successfully
-in rocket-chip/emulator: make, make run and make debug (same in vsim).
-in fpga-zynq/zedboard: make rocket and make project successfully
from fpga-zynq.
davidbiancolin
commented on May 18, 2024
There is no Makefile in the root of this repository. You need to cd into zedboard/ first, before calling make init-submodules. If you do this you won't need to init the submodule manually. Also, you don't need to make anything in rocket-chip, aside from the toolchain if you don't already have one and need to compile new binaries.
This should be sufficient to produce an updated boot.bin with the newly compiled bitstream.
cd zedboard
make init-submodules
make
Can you just attach the entire log?
from fpga-zynq.
ninode
commented on May 18, 2024
Ok, I'll retry. Thank you.
Here's the entire log file:
It's too long, so it takes 3 comments for it to upload.
#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
# Start of session at: Wed Jul 12 06:40:36 2017
# Process ID: 14353
# Current directory: /home/alpha/fpga-zynq/zedboard
# Command line: vivado -mode tcl -source src/tcl/make_bitstream_ZynqConfig.tcl
# Log file: /home/alpha/fpga-zynq/zedboard/vivado.log
# Journal file: /home/alpha/fpga-zynq/zedboard/vivado.jou
#-----------------------------------------------------------
source src/tcl/make_bitstream_ZynqConfig.tcl
# open_project zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/alpha/Xilinx/Vivado/2016.2/data/ip'.
# reset_run synth_1
# reset_run impl_1
# launch_runs synth_1
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Successfully read diagram <system> from BD file </home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/system.bd>
Verilog Output written to : /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote : </home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/system.bd>
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
WARNING: [xilinx.com:ip:processing_system7:5.5-1] system_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_pc .
INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_1/s00_couplers/auto_pc .
Exporting to file /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hw_handoff/system.hwh
Generated Block Design Tcl file /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hw_handoff/system_bd.tcl
Generated Hardware Definition File /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.hwdef
INFO: [HDL 9-2216] Analyzing Verilog file "/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v" into library work [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v" into library work [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:1]
INFO: [HDL 9-1065] Parsing verilog file "/home/alpha/fpga-zynq/zedboard/src/verilog/clocking.vh" included at line 2. [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:2]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v" into library work [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1]
[Wed Jul 12 06:41:22 2017] Launched synth_1...
Run output will be captured here: /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1261.348 ; gain = 259.125 ; free physical = 142 ; free virtual = 5079
# wait_on_run synth_1
[Wed Jul 12 06:41:22 2017] Waiting for synth_1 to finish...
*** Running vivado
with args -log rocketchip_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source rocketchip_wrapper.tcl
****** Vivado v2016.2 (64-bit)
**** SW Build 1577090 on Thu Jun 2 16:32:35 MDT 2016
**** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
source rocketchip_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/alpha/Xilinx/Vivado/2016.2/data/ip'.
Command: synth_design -top rocketchip_wrapper -part xc7z020clg484-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 14502
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1129.719 ; gain = 246.684 ; free physical = 78 ; free virtual = 4776
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'rocketchip_wrapper' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:4]
INFO: [Synth 8-638] synthesizing module 'system' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:823]
INFO: [Synth 8-638] synthesizing module 'system_axi_interconnect_0_0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1569]
INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_Y9JEWS' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:417]
INFO: [Synth 8-638] synthesizing module 'system_auto_pc_0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:58]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_axi_protocol_converter' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_M_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_S_AXI_PROTOCOL bound to: 1 - type: integer
Parameter C_IGNORE_ID bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 12 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_TRANSLATION_MODE bound to: 2 - type: integer
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_AXILITE_SIZE bound to: 3'b010
Parameter P_INCR bound to: 2'b01
Parameter P_DECERR bound to: 2'b11
Parameter P_SLVERR bound to: 2'b10
Parameter P_PROTECTION bound to: 1 - type: integer
Parameter P_CONVERSION bound to: 2 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_axi_protocol_converter' (1#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
INFO: [Synth 8-256] done synthesizing module 'system_auto_pc_0' (2#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:58]
INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_Y9JEWS' (3#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:417]
INFO: [Synth 8-256] done synthesizing module 'system_axi_interconnect_0_0' (4#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1569]
INFO: [Synth 8-638] synthesizing module 'system_axi_interconnect_1_0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1984]
INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_8CNLH6' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:12]
INFO: [Synth 8-638] synthesizing module 'system_auto_pc_1' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_auto_pc_1/synth/system_auto_pc_1.v:58]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_axi_protocol_converter__parameterized0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_M_AXI_PROTOCOL bound to: 1 - type: integer
Parameter C_S_AXI_PROTOCOL bound to: 0 - type: integer
Parameter C_IGNORE_ID bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_TRANSLATION_MODE bound to: 2 - type: integer
Parameter P_AXI4 bound to: 0 - type: integer
Parameter P_AXI3 bound to: 1 - type: integer
Parameter P_AXILITE bound to: 2 - type: integer
Parameter P_AXILITE_SIZE bound to: 3'b011
Parameter P_INCR bound to: 2'b01
Parameter P_DECERR bound to: 2'b11
Parameter P_SLVERR bound to: 2'b10
Parameter P_PROTECTION bound to: 1 - type: integer
Parameter P_CONVERSION bound to: 2 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_axi3_conv' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v:69]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer
Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer
Parameter C_SUPPORT_SPLITTING bound to: 1 - type: integer
Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer
Parameter C_SINGLE_THREAD bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_b_downsizer' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v:65]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_RESP_OKAY bound to: 2'b00
Parameter C_RESP_EXOKAY bound to: 2'b01
Parameter C_RESP_SLVERROR bound to: 2'b10
Parameter C_RESP_DECERR bound to: 2'b11
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_b_downsizer' (5#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v:65]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_a_axi3_conv' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:62]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_CHANNEL bound to: 0 - type: integer
Parameter C_SUPPORT_SPLITTING bound to: 1 - type: integer
Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer
Parameter C_SINGLE_THREAD bound to: 1 - type: integer
Parameter C_FIX_BURST bound to: 2'b00
Parameter C_INCR_BURST bound to: 2'b01
Parameter C_WRAP_BURST bound to: 2'b10
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_SIZE_MASK bound to: 40'b1111111111111111111111111111111100000000
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 10 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 10 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_WR_RST_MAXFAN bound to: 3 - type: integer
Parameter C_RD_RST_MAXFAN bound to: 3 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 10 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_WIDTH bound to: 5 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_WR_RD_RATIO bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DIN_WIDTH bound to: 10 - type: integer
Parameter C_DOUT_WIDTH bound to: 10 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 10 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen' (23#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo' (24#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo__parameterized0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 5 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen__parameterized0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 5 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 5 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DIN_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 5 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 5 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen__parameterized0' (24#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo__parameterized0' (24#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_a_axi3_conv' (25#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_w_axi3_conv' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v:61]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_SUPPORT_SPLITTING bound to: 1 - type: integer
Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_w_axi3_conv' (26#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v:61]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_a_axi3_conv__parameterized0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:62]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_AUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_CHANNEL bound to: 1 - type: integer
Parameter C_SUPPORT_SPLITTING bound to: 1 - type: integer
Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer
Parameter C_SINGLE_THREAD bound to: 1 - type: integer
Parameter C_FIX_BURST bound to: 2'b00
Parameter C_INCR_BURST bound to: 2'b01
Parameter C_WRAP_BURST bound to: 2'b10
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_SIZE_MASK bound to: 40'b1111111111111111111111111111111100000000
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo__parameterized1' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 1 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
INFO: [Synth 8-638] synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen__parameterized1' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer
Parameter C_FIFO_WIDTH bound to: 1 - type: integer
Parameter C_FIFO_TYPE bound to: lut - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_AXI_WR_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_AXI_RD_CHANNEL bound to: 0 - type: integer
Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer
Parameter C_HAS_MASTER_CE bound to: 0 - type: integer
Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer
Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer
Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer
Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer
Parameter C_AXI_LOCK_WIDTH bound to: 2 - type: integer
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer
Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer
Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_HAS_AXIS_TDATA bound to: 0 - type: integer
Parameter C_HAS_AXIS_TID bound to: 0 - type: integer
Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TUSER bound to: 0 - type: integer
Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer
Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer
Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer
Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer
Parameter C_AXIS_TDATA_WIDTH bound to: 64 - type: integer
Parameter C_AXIS_TID_WIDTH bound to: 8 - type: integer
Parameter C_AXIS_TDEST_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TSTRB_WIDTH bound to: 4 - type: integer
Parameter C_AXIS_TKEEP_WIDTH bound to: 4 - type: integer
Parameter C_WACH_TYPE bound to: 0 - type: integer
Parameter C_WDCH_TYPE bound to: 0 - type: integer
Parameter C_WRCH_TYPE bound to: 0 - type: integer
Parameter C_RACH_TYPE bound to: 0 - type: integer
Parameter C_RDCH_TYPE bound to: 0 - type: integer
Parameter C_AXIS_TYPE bound to: 0 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer
Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 512x36 - type: string
Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 512x36 - type: string
Parameter C_USE_ECC_WACH bound to: 0 - type: integer
Parameter C_USE_ECC_WDCH bound to: 0 - type: integer
Parameter C_USE_ECC_WRCH bound to: 0 - type: integer
Parameter C_USE_ECC_RACH bound to: 0 - type: integer
Parameter C_USE_ECC_RDCH bound to: 0 - type: integer
Parameter C_USE_ECC_AXIS bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer
Parameter C_DIN_WIDTH_WACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer
Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer
Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer
Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer
Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer
Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer
Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer
Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer
Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer
Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer
Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer
Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer
Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer
Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer
Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_HAS_WR_RST bound to: 0 - type: integer
Parameter C_HAS_RD_RST bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0 - type: string
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_COUNT_TYPE bound to: 0 - type: integer
Parameter C_DEFAULT_VALUE bound to: BlankString - type: string
Parameter C_ENABLE_RLOCS bound to: 0 - type: integer
Parameter C_HAS_BACKUP bound to: 0 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer
Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer
Parameter C_MIF_FILE_NAME bound to: BlankString - type: string
Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer
Parameter C_RD_FREQ bound to: 1 - type: integer
Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer
Parameter C_WR_FREQ bound to: 1 - type: integer
Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_FULL_FLAGS_RST_VAL bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_MSGON_VAL bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 4 - type: integer
Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 5 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 31 - type: integer
Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 30 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_VALID_LOW bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_WR_ACK_LOW bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_OVERFLOW_LOW bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_AXI_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_HAS_INT_CLK bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 1 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
Parameter C_USE_INPUT_CE bound to: 0 - type: integer
Parameter C_USE_OUTPUT_CE bound to: 0 - type: integer
Parameter C_USE_SYNC_CLK bound to: 0 - type: integer
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_USE_DOUT_RST bound to: 0 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_MEMORY_TYPE bound to: 2 - type: integer
Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer
Parameter C_PRELOAD_REGS bound to: 1 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_RD_DEPTH bound to: 32 - type: integer
Parameter C_WR_DEPTH bound to: 32 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer
Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer
Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_HAS_RST bound to: 1 - type: integer
Parameter C_HAS_SRST bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_RST_VAL bound to: 0000 - type: string
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_LARGER_DEPTH bound to: 32 - type: integer
Parameter C_DEPTH_RATIO_RD bound to: 1 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_SMALLER_DATA_WIDTH bound to: 1 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_COMMON_CLOCK bound to: 1 - type: integer
Parameter C_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_DIN_WIDTH bound to: 1 - type: integer
Parameter C_DOUT_WIDTH bound to: 1 - type: integer
Parameter C_PKTFIFO_DATA_WIDTH bound to: 1 - type: integer
Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer
Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer
Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_OVERFLOW bound to: 0 - type: integer
Parameter C_HAS_RD_DATA_COUNT bound to: 0 - type: integer
Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer
Parameter C_HAS_VALID bound to: 0 - type: integer
Parameter C_HAS_WR_ACK bound to: 0 - type: integer
Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer
Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer
Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer
Parameter C_DEPTH_RATIO_WR bound to: 1 - type: integer
Parameter C_RD_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_RD_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_PNTR_WIDTH bound to: 5 - type: integer
Parameter C_WR_DATA_COUNT_WIDTH bound to: 6 - type: integer
Parameter C_USE_FWFT_DATA_COUNT bound to: 1 - type: integer
Parameter C_USE_ECC bound to: 0 - type: integer
Parameter C_FIFO_TYPE bound to: 0 - type: integer
Parameter C_BYTE_STRB_WIDTH bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_fifo_gen__parameterized1' (26#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v:60]
INFO: [Synth 8-256] done synthesizing module 'axi_data_fifo_v2_1_8_axic_fifo__parameterized1' (26#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v:64]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_a_axi3_conv__parameterized0' (26#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:62]
INFO: [Synth 8-638] synthesizing module 'axi_protocol_converter_v2_1_9_r_axi3_conv' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v:61]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer
Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer
Parameter C_SUPPORT_SPLITTING bound to: 1 - type: integer
Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer
Parameter C_RESP_OKAY bound to: 2'b00
Parameter C_RESP_EXOKAY bound to: 2'b01
Parameter C_RESP_SLVERROR bound to: 2'b10
Parameter C_RESP_DECERR bound to: 2'b11
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_r_axi3_conv' (27#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v:61]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_axi3_conv' (28#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi3_conv.v:69]
INFO: [Synth 8-256] done synthesizing module 'axi_protocol_converter_v2_1_9_axi_protocol_converter__parameterized0' (28#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v:62]
INFO: [Synth 8-256] done synthesizing module 'system_auto_pc_1' (29#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_auto_pc_1/synth/system_auto_pc_1.v:58]
INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_8CNLH6' (30#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:12]
INFO: [Synth 8-256] done synthesizing module 'system_axi_interconnect_1_0' (31#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1984]
INFO: [Synth 8-638] synthesizing module 'system_proc_sys_reset_0_0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/synth/system_proc_sys_reset_0_0.vhd:71]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:140' bound to instance 'U0' of component 'proc_sys_reset' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/synth/system_proc_sys_reset_0_0.vhd:116]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:138]
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
INFO: [Synth 8-3491] module 'SRL16' declared at '/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:43294' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:190]
INFO: [Synth 8-638] synthesizing module 'SRL16' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:43294]
Parameter INIT bound to: 16'b0000000000000000
INFO: [Synth 8-256] done synthesizing module 'SRL16' (32#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:43294]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (33#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (34#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd:138]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:146]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:125]
Parameter C_SIZE bound to: 6 - type: integer
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (35#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd:125]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (36#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:146]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (37#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd:199]
INFO: [Synth 8-256] done synthesizing module 'system_proc_sys_reset_0_0' (38#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/synth/system_proc_sys_reset_0_0.vhd:71]
WARNING: [Synth 8-350] instance 'proc_sys_reset_0' of module 'system_proc_sys_reset_0_0' requires 10 connections, but only 7 given [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1455]
INFO: [Synth 8-638] synthesizing module 'system_processing_system7_0_0' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:59]
INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:156]
Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
Parameter C_FCLK_CLK0_BUF bound to: true - type: string
Parameter C_FCLK_CLK1_BUF bound to: false - type: string
Parameter C_FCLK_CLK2_BUF bound to: false - type: string
Parameter C_FCLK_CLK3_BUF bound to: false - type: string
Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
Parameter C_DQ_WIDTH bound to: 32 - type: integer
Parameter C_DQS_WIDTH bound to: 4 - type: integer
Parameter C_DM_WIDTH bound to: 4 - type: integer
Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
Parameter C_PACKAGE_NAME bound to: clg484 - type: string
Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP0 bound to: 1 - type: integer
Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
from fpga-zynq.
ninode
commented on May 18, 2024
log 2
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1338]
INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1339]
INFO: [Synth 8-638] synthesizing module 'BUFG' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (39#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-638] synthesizing module 'BIBUF' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:268]
INFO: [Synth 8-256] done synthesizing module 'BIBUF' (40#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:268]
INFO: [Synth 8-638] synthesizing module 'PS7' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:33164]
INFO: [Synth 8-256] done synthesizing module 'PS7' (41#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:33164]
INFO: [Synth 8-256] done synthesizing module 'processing_system7_v5_5_processing_system7' (42#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:156]
WARNING: [Synth 8-350] instance 'inst' of module 'processing_system7_v5_5_processing_system7' requires 685 connections, but only 672 given [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:453]
INFO: [Synth 8-256] done synthesizing module 'system_processing_system7_0_0' (43#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:59]
WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'system_processing_system7_0_0' requires 113 connections, but only 103 given [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:1463]
INFO: [Synth 8-256] done synthesizing module 'system' (44#1) [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/hdl/system.v:823]
INFO: [Synth 8-638] synthesizing module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:186516]
INFO: [Synth 8-638] synthesizing module 'FPGAZynqTop' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:175498]
INFO: [Synth 8-638] synthesizing module 'TLXbar_socBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:14]
WARNING: [Synth 8-3848] Net _GEN_2 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:293]
WARNING: [Synth 8-3848] Net _GEN_3 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:295]
WARNING: [Synth 8-3848] Net _GEN_4 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:297]
WARNING: [Synth 8-3848] Net _GEN_5 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:299]
WARNING: [Synth 8-3848] Net _GEN_6 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:301]
WARNING: [Synth 8-3848] Net _GEN_7 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:303]
WARNING: [Synth 8-3848] Net _GEN_8 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:305]
WARNING: [Synth 8-3848] Net _GEN_18 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:325]
WARNING: [Synth 8-3848] Net _GEN_19 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:327]
WARNING: [Synth 8-3848] Net _GEN_17 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:323]
WARNING: [Synth 8-3848] Net _GEN_9 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:307]
WARNING: [Synth 8-3848] Net _GEN_10 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:309]
WARNING: [Synth 8-3848] Net _GEN_11 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:311]
WARNING: [Synth 8-3848] Net _GEN_12 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:313]
WARNING: [Synth 8-3848] Net _GEN_13 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:315]
WARNING: [Synth 8-3848] Net _GEN_14 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:317]
WARNING: [Synth 8-3848] Net _GEN_15 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:319]
WARNING: [Synth 8-3848] Net _GEN_16 in module/entity TLXbar_socBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:321]
INFO: [Synth 8-256] done synthesizing module 'TLXbar_socBus' (45#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:14]
INFO: [Synth 8-638] synthesizing module 'TLXbar_peripheryBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:783]
WARNING: [Synth 8-3848] Net _GEN_3 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1322]
WARNING: [Synth 8-3848] Net _GEN_4 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1324]
WARNING: [Synth 8-3848] Net _GEN_5 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1326]
WARNING: [Synth 8-3848] Net _GEN_6 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1328]
WARNING: [Synth 8-3848] Net _GEN_7 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1330]
WARNING: [Synth 8-3848] Net _GEN_8 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1332]
WARNING: [Synth 8-3848] Net _GEN_9 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1334]
WARNING: [Synth 8-3848] Net _GEN_28 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1372]
WARNING: [Synth 8-3848] Net _GEN_29 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1374]
WARNING: [Synth 8-3848] Net _GEN_30 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1376]
WARNING: [Synth 8-3848] Net _GEN_31 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1378]
WARNING: [Synth 8-3848] Net _GEN_26 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1368]
WARNING: [Synth 8-3848] Net _GEN_10 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1336]
WARNING: [Synth 8-3848] Net _GEN_11 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1338]
WARNING: [Synth 8-3848] Net _GEN_12 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1340]
WARNING: [Synth 8-3848] Net _GEN_13 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1342]
WARNING: [Synth 8-3848] Net _GEN_14 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1344]
WARNING: [Synth 8-3848] Net _GEN_15 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1346]
WARNING: [Synth 8-3848] Net _GEN_16 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1348]
WARNING: [Synth 8-3848] Net _GEN_27 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1370]
WARNING: [Synth 8-3848] Net _GEN_18 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1352]
WARNING: [Synth 8-3848] Net _GEN_19 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1354]
WARNING: [Synth 8-3848] Net _GEN_20 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1356]
WARNING: [Synth 8-3848] Net _GEN_21 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1358]
WARNING: [Synth 8-3848] Net _GEN_22 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1360]
WARNING: [Synth 8-3848] Net _GEN_23 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1362]
WARNING: [Synth 8-3848] Net _GEN_24 in module/entity TLXbar_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:1364]
INFO: [Synth 8-256] done synthesizing module 'TLXbar_peripheryBus' (46#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:783]
INFO: [Synth 8-638] synthesizing module 'TLLegacy_legacy' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2191]
WARNING: [Synth 8-3848] Net _GEN_10 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2695]
WARNING: [Synth 8-3848] Net _GEN_17 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2709]
WARNING: [Synth 8-3848] Net _GEN_11 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2697]
WARNING: [Synth 8-3848] Net _GEN_18 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2711]
WARNING: [Synth 8-3848] Net _GEN_12 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2699]
WARNING: [Synth 8-3848] Net _GEN_19 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2713]
WARNING: [Synth 8-3848] Net _GEN_14 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2703]
WARNING: [Synth 8-3848] Net _GEN_21 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2717]
WARNING: [Synth 8-3848] Net _GEN_15 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2705]
WARNING: [Synth 8-3848] Net _GEN_22 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2719]
WARNING: [Synth 8-3848] Net _GEN_2 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2679]
WARNING: [Synth 8-3848] Net _GEN_3 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2681]
WARNING: [Synth 8-3848] Net _GEN_4 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2683]
WARNING: [Synth 8-3848] Net _GEN_5 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2685]
WARNING: [Synth 8-3848] Net _GEN_6 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2687]
WARNING: [Synth 8-3848] Net _GEN_7 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2689]
WARNING: [Synth 8-3848] Net _GEN_8 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2691]
WARNING: [Synth 8-3848] Net _GEN_9 in module/entity TLLegacy_legacy does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2693]
INFO: [Synth 8-256] done synthesizing module 'TLLegacy_legacy' (47#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:2191]
INFO: [Synth 8-638] synthesizing module 'TLAtomicAutomata_peripheryBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:3308]
WARNING: [Synth 8-3848] Net _GEN_40 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4213]
WARNING: [Synth 8-3848] Net _GEN_41 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4215]
WARNING: [Synth 8-3848] Net _GEN_42 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4217]
WARNING: [Synth 8-3848] Net _GEN_43 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4219]
WARNING: [Synth 8-3848] Net _GEN_44 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4221]
WARNING: [Synth 8-3848] Net _GEN_45 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4223]
WARNING: [Synth 8-3848] Net _GEN_46 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4225]
WARNING: [Synth 8-3848] Net _GEN_47 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4227]
WARNING: [Synth 8-3848] Net _GEN_48 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4229]
WARNING: [Synth 8-3848] Net _GEN_49 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4231]
WARNING: [Synth 8-3848] Net _GEN_50 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4233]
WARNING: [Synth 8-3848] Net _GEN_51 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4235]
WARNING: [Synth 8-3848] Net _GEN_52 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4237]
WARNING: [Synth 8-3848] Net _GEN_53 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4239]
WARNING: [Synth 8-3848] Net _GEN_54 in module/entity TLAtomicAutomata_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4241]
INFO: [Synth 8-256] done synthesizing module 'TLAtomicAutomata_peripheryBus' (48#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:3308]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:178812]
INFO: [Synth 8-638] synthesizing module 'TLMonitor' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:5393]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor' (49#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:5393]
INFO: [Synth 8-638] synthesizing module 'TLBuffer_peripheryBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11121]
INFO: [Synth 8-638] synthesizing module 'Queue' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:10534]
INFO: [Synth 8-256] done synthesizing module 'Queue' (50#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:10534]
INFO: [Synth 8-638] synthesizing module 'Queue_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:10815]
INFO: [Synth 8-256] done synthesizing module 'Queue_1' (51#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:10815]
WARNING: [Synth 8-3848] Net _GEN_0 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11249]
WARNING: [Synth 8-3848] Net _GEN_1 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11251]
WARNING: [Synth 8-3848] Net _GEN_2 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11253]
WARNING: [Synth 8-3848] Net _GEN_3 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11255]
WARNING: [Synth 8-3848] Net _GEN_4 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11257]
WARNING: [Synth 8-3848] Net _GEN_5 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11259]
WARNING: [Synth 8-3848] Net _GEN_6 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11261]
WARNING: [Synth 8-3848] Net _GEN_7 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11263]
WARNING: [Synth 8-3848] Net _GEN_8 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11265]
WARNING: [Synth 8-3848] Net _GEN_9 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11267]
WARNING: [Synth 8-3848] Net _GEN_10 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11269]
WARNING: [Synth 8-3848] Net _GEN_11 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11271]
WARNING: [Synth 8-3848] Net _GEN_12 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11273]
WARNING: [Synth 8-3848] Net _GEN_13 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11275]
WARNING: [Synth 8-3848] Net _GEN_14 in module/entity TLBuffer_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11277]
INFO: [Synth 8-256] done synthesizing module 'TLBuffer_peripheryBus' (52#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11121]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:178940]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11459]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_1' (53#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:11459]
INFO: [Synth 8-638] synthesizing module 'TLWidthWidget_peripheryBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16755]
INFO: [Synth 8-638] synthesizing module 'Repeater' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16582]
INFO: [Synth 8-256] done synthesizing module 'Repeater' (54#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16582]
WARNING: [Synth 8-3848] Net _GEN_15 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16987]
WARNING: [Synth 8-3848] Net _GEN_16 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16989]
WARNING: [Synth 8-3848] Net _GEN_17 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16991]
WARNING: [Synth 8-3848] Net _GEN_18 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16993]
WARNING: [Synth 8-3848] Net _GEN_19 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16995]
WARNING: [Synth 8-3848] Net _GEN_20 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16997]
WARNING: [Synth 8-3848] Net _GEN_21 in module/entity TLWidthWidget_peripheryBus does not have driver. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16999]
INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'TLWidthWidget_peripheryBus' (55#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:16755]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179068]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:17320]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_2' (56#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:17320]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179112]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:22407]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_3' (57#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:22407]
INFO: [Synth 8-638] synthesizing module 'TLHintHandler_peripheryBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:27366]
INFO: [Synth 8-256] done synthesizing module 'TLHintHandler_peripheryBus' (58#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:27366]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179240]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:27928]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_4' (59#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:27928]
INFO: [Synth 8-638] synthesizing module 'TLWidthWidget_peripheryBus_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:33041]
INFO: [Synth 8-256] done synthesizing module 'TLWidthWidget_peripheryBus_1' (60#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:33041]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179368]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_5' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:33264]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_5' (61#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:33264]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179412]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_6' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:38405]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_6' (62#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:38405]
INFO: [Synth 8-638] synthesizing module 'TLROM_bootrom' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:43546]
INFO: [Synth 8-256] done synthesizing module 'TLROM_bootrom' (63#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:43546]
INFO: [Synth 8-638] synthesizing module 'TLFragmenter_bootrom' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:47950]
INFO: [Synth 8-638] synthesizing module 'Repeater_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:47777]
INFO: [Synth 8-256] done synthesizing module 'Repeater_1' (64#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:47777]
INFO: [Synth 8-256] done synthesizing module 'TLFragmenter_bootrom' (65#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:47950]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179584]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_7' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:48489]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_7' (66#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:48489]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179628]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_8' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:53330]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_8' (67#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:53330]
INFO: [Synth 8-638] synthesizing module 'CoreplexLocalInterrupter_clint' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:58159]
INFO: [Synth 8-256] done synthesizing module 'CoreplexLocalInterrupter_clint' (68#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:58159]
INFO: [Synth 8-638] synthesizing module 'TLWidthWidget_clint' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:59003]
INFO: [Synth 8-638] synthesizing module 'Repeater_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:58814]
INFO: [Synth 8-256] done synthesizing module 'Repeater_2' (69#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:58814]
INFO: [Synth 8-256] done synthesizing module 'TLWidthWidget_clint' (70#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:59003]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179803]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_9' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:59775]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_9' (71#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:59775]
INFO: [Synth 8-638] synthesizing module 'TLFragmenter_clint' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:64664]
INFO: [Synth 8-256] done synthesizing module 'TLFragmenter_clint' (72#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:64664]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179931]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_10' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:65245]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_10' (73#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:65245]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179975]
INFO: [Synth 8-638] synthesizing module 'TLMonitor_11' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:70262]
INFO: [Synth 8-256] done synthesizing module 'TLMonitor_11' (74#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:70262]
INFO: [Synth 8-638] synthesizing module 'DefaultCoreplex' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168888]
INFO: [Synth 8-638] synthesizing module 'RocketTile' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:128125]
INFO: [Synth 8-638] synthesizing module 'Rocket' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:85283]
INFO: [Synth 8-638] synthesizing module 'IBuf' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:76441]
INFO: [Synth 8-638] synthesizing module 'RVCExpander' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:75219]
INFO: [Synth 8-256] done synthesizing module 'RVCExpander' (75#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:75219]
INFO: [Synth 8-256] done synthesizing module 'IBuf' (76#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:76441]
INFO: [Synth 8-638] synthesizing module 'CSRFile' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:77093]
INFO: [Synth 8-4471] merging register 'reg_bp_0_control_chain_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79778]
INFO: [Synth 8-4471] merging register 'reg_bp_0_control_h_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79782]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_dmode_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80303]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_reserved_reg[39:0]' into 'reg_bp_0_control_reserved_reg[39:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80305]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_action_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80306]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_chain_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80307]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_zero_reg[1:0]' into 'reg_bp_0_control_zero_reg[1:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80308]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_tmatch_reg[1:0]' into 'reg_bp_0_control_zero_reg[1:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80309]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_m_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80310]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_h_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80311]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_s_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80312]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_u_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80313]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_x_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80314]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_w_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80315]
INFO: [Synth 8-4471] merging register 'reg_bp_1_control_r_reg' into 'reg_tselect_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80316]
INFO: [Synth 8-256] done synthesizing module 'CSRFile' (77#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:77093]
INFO: [Synth 8-638] synthesizing module 'BreakpointUnit' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:83503]
INFO: [Synth 8-256] done synthesizing module 'BreakpointUnit' (78#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:83503]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:83663]
INFO: [Synth 8-256] done synthesizing module 'ALU' (79#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:83663]
INFO: [Synth 8-638] synthesizing module 'MulDiv' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:84014]
INFO: [Synth 8-256] done synthesizing module 'MulDiv' (80#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:84014]
INFO: [Synth 8-256] done synthesizing module 'Rocket' (81#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:85283]
INFO: [Synth 8-638] synthesizing module 'Frontend' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:99294]
INFO: [Synth 8-638] synthesizing module 'ICache' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91250]
INFO: [Synth 8-638] synthesizing module 'FlowThroughSerializer' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91217]
INFO: [Synth 8-256] done synthesizing module 'FlowThroughSerializer' (82#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91217]
INFO: [Synth 8-256] done synthesizing module 'ICache' (83#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91250]
INFO: [Synth 8-638] synthesizing module 'TLB' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:92323]
INFO: [Synth 8-256] done synthesizing module 'TLB' (84#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:92323]
INFO: [Synth 8-638] synthesizing module 'BTB' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:93534]
INFO: [Synth 8-256] done synthesizing module 'BTB' (85#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:93534]
INFO: [Synth 8-256] done synthesizing module 'Frontend' (86#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:99294]
INFO: [Synth 8-638] synthesizing module 'HellaCache' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:107046]
INFO: [Synth 8-638] synthesizing module 'WritebackUnit' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100236]
INFO: [Synth 8-256] done synthesizing module 'WritebackUnit' (87#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100236]
INFO: [Synth 8-638] synthesizing module 'ProbeUnit' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100565]
INFO: [Synth 8-256] done synthesizing module 'ProbeUnit' (88#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100565]
INFO: [Synth 8-638] synthesizing module 'MSHRFile' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:104241]
INFO: [Synth 8-638] synthesizing module 'Arbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100905]
INFO: [Synth 8-256] done synthesizing module 'Arbiter' (89#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100905]
INFO: [Synth 8-638] synthesizing module 'Arbiter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100949]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_1' (90#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100949]
INFO: [Synth 8-638] synthesizing module 'LockingArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100999]
INFO: [Synth 8-256] done synthesizing module 'LockingArbiter' (91#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:100999]
INFO: [Synth 8-638] synthesizing module 'Arbiter_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101319]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_2' (92#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101319]
INFO: [Synth 8-638] synthesizing module 'Arbiter_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101374]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_3' (93#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101374]
INFO: [Synth 8-638] synthesizing module 'Arbiter_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101442]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_4' (94#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101442]
INFO: [Synth 8-638] synthesizing module 'Arbiter_5' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101504]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_5' (95#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101504]
INFO: [Synth 8-638] synthesizing module 'MSHR' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101900]
INFO: [Synth 8-638] synthesizing module 'Queue_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101536]
INFO: [Synth 8-256] done synthesizing module 'Queue_2' (96#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101536]
INFO: [Synth 8-638] synthesizing module 'FinishQueue' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101792]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_manager_xact_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_manager_xact_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_manager_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_manager_id_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'FinishQueue' (97#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101792]
INFO: [Synth 8-256] done synthesizing module 'MSHR' (98#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:101900]
INFO: [Synth 8-638] synthesizing module 'MSHR_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:102780]
INFO: [Synth 8-256] done synthesizing module 'MSHR_1' (99#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:102780]
INFO: [Synth 8-638] synthesizing module 'Arbiter_6' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103660]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_6' (100#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103660]
INFO: [Synth 8-638] synthesizing module 'Arbiter_7' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103676]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_7' (101#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103676]
INFO: [Synth 8-638] synthesizing module 'IOMSHR' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103716]
INFO: [Synth 8-256] done synthesizing module 'IOMSHR' (102#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103716]
INFO: [Synth 8-256] done synthesizing module 'MSHRFile' (103#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:104241]
INFO: [Synth 8-638] synthesizing module 'MetadataArray' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105742]
INFO: [Synth 8-256] done synthesizing module 'MetadataArray' (104#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105742]
INFO: [Synth 8-638] synthesizing module 'Arbiter_8' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106032]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_8' (105#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106032]
INFO: [Synth 8-638] synthesizing module 'DataArray' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106121]
INFO: [Synth 8-256] done synthesizing module 'DataArray' (106#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106121]
INFO: [Synth 8-638] synthesizing module 'Arbiter_10' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106408]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_10' (107#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106408]
INFO: [Synth 8-638] synthesizing module 'Arbiter_11' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106480]
INFO: [Synth 8-256] done synthesizing module 'Arbiter_11' (108#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106480]
INFO: [Synth 8-638] synthesizing module 'AMOALU' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106530]
INFO: [Synth 8-256] done synthesizing module 'AMOALU' (109#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106530]
INFO: [Synth 8-638] synthesizing module 'LockingArbiter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106768]
INFO: [Synth 8-256] done synthesizing module 'LockingArbiter_1' (110#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:106768]
INFO: [Synth 8-638] synthesizing module 'FlowThroughSerializer_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:107010]
INFO: [Synth 8-256] done synthesizing module 'FlowThroughSerializer_1' (111#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:107010]
INFO: [Synth 8-256] done synthesizing module 'HellaCache' (112#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:107046]
INFO: [Synth 8-638] synthesizing module 'FPU' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122621]
INFO: [Synth 8-638] synthesizing module 'FPUDecoder' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:109986]
INFO: [Synth 8-256] done synthesizing module 'FPUDecoder' (113#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:109986]
INFO: [Synth 8-638] synthesizing module 'FPUFMAPipe' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:111874]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:111726]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN_preMul' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:110198]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN_preMul' (114#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:110198]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN_postMul' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:110546]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN_postMul' (115#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:110546]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN' (116#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:111726]
INFO: [Synth 8-256] done synthesizing module 'FPUFMAPipe' (117#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:111874]
INFO: [Synth 8-638] synthesizing module 'FPToInt' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112918]
INFO: [Synth 8-638] synthesizing module 'CompareRecFN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112306]
INFO: [Synth 8-256] done synthesizing module 'CompareRecFN' (118#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112306]
INFO: [Synth 8-638] synthesizing module 'RecFNToIN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112502]
INFO: [Synth 8-256] done synthesizing module 'RecFNToIN' (119#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112502]
INFO: [Synth 8-638] synthesizing module 'RecFNToIN_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112710]
INFO: [Synth 8-256] done synthesizing module 'RecFNToIN_1' (120#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112710]
INFO: [Synth 8-256] done synthesizing module 'FPToInt' (121#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112918]
INFO: [Synth 8-638] synthesizing module 'IntToFP' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:114634]
INFO: [Synth 8-638] synthesizing module 'INToRecFN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:113786]
INFO: [Synth 8-256] done synthesizing module 'INToRecFN' (122#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:113786]
INFO: [Synth 8-638] synthesizing module 'INToRecFN_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:114210]
INFO: [Synth 8-256] done synthesizing module 'INToRecFN_1' (123#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:114210]
INFO: [Synth 8-256] done synthesizing module 'IntToFP' (124#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:114634]
INFO: [Synth 8-638] synthesizing module 'FPToFP' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116349]
INFO: [Synth 8-638] synthesizing module 'RecFNToRecFN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116094]
INFO: [Synth 8-638] synthesizing module 'RoundRawFNToRecFN' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:115718]
INFO: [Synth 8-256] done synthesizing module 'RoundRawFNToRecFN' (125#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:115718]
INFO: [Synth 8-256] done synthesizing module 'RecFNToRecFN' (126#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116094]
INFO: [Synth 8-638] synthesizing module 'RecFNToRecFN_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116230]
INFO: [Synth 8-256] done synthesizing module 'RecFNToRecFN_1' (127#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116230]
INFO: [Synth 8-256] done synthesizing module 'FPToFP' (128#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116349]
INFO: [Synth 8-638] synthesizing module 'FPUFMAPipe_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:119118]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:118970]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN_preMul_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116908]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN_preMul_1' (129#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116908]
INFO: [Synth 8-638] synthesizing module 'MulAddRecFN_postMul_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:117298]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN_postMul_1' (130#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:117298]
INFO: [Synth 8-256] done synthesizing module 'MulAddRecFN_1' (131#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:118970]
INFO: [Synth 8-256] done synthesizing module 'FPUFMAPipe_1' (132#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:119118]
INFO: [Synth 8-638] synthesizing module 'DivSqrtRecF64' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122519]
INFO: [Synth 8-638] synthesizing module 'DivSqrtRecF64_mulAddZ31' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:119583]
INFO: [Synth 8-256] done synthesizing module 'DivSqrtRecF64_mulAddZ31' (133#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:119583]
INFO: [Synth 8-638] synthesizing module 'Mul54' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122411]
INFO: [Synth 8-256] done synthesizing module 'Mul54' (134#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122411]
INFO: [Synth 8-256] done synthesizing module 'DivSqrtRecF64' (135#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122519]
WARNING: [Synth 8-4767] Trying to implement RAM 'regfile_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
2: Unable to determine number of words or word size in RAM.
3: No valid read/write found for RAM.
RAM "regfile_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'FPU' (136#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:122621]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIOArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125656]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIOArbiter' (137#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125656]
INFO: [Synth 8-638] synthesizing module 'PTW' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125925]
INFO: [Synth 8-638] synthesizing module 'RRArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125712]
INFO: [Synth 8-256] done synthesizing module 'RRArbiter' (138#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125712]
INFO: [Synth 8-256] done synthesizing module 'PTW' (139#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:125925]
INFO: [Synth 8-638] synthesizing module 'HellaCacheArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:127910]
INFO: [Synth 8-256] done synthesizing module 'HellaCacheArbiter' (140#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:127910]
INFO: [Synth 8-256] done synthesizing module 'RocketTile' (141#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:128125]
INFO: [Synth 8-638] synthesizing module 'PortedTileLinkCrossbar' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136514]
INFO: [Synth 8-638] synthesizing module 'TileLinkEnqueuer' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:130758]
INFO: [Synth 8-256] done synthesizing module 'TileLinkEnqueuer' (142#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:130758]
INFO: [Synth 8-638] synthesizing module 'ClientTileLinkNetworkPort' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:130889]
INFO: [Synth 8-256] done synthesizing module 'ClientTileLinkNetworkPort' (143#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:130889]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkNetworkPort' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131418]
INFO: [Synth 8-638] synthesizing module 'FinishUnit' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131267]
INFO: [Synth 8-638] synthesizing module 'FinishQueue_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131111]
INFO: [Synth 8-256] done synthesizing module 'FinishQueue_3' (144#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131111]
INFO: [Synth 8-256] done synthesizing module 'FinishUnit' (145#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131267]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkNetworkPort' (146#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131418]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkNetworkPort_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131827]
INFO: [Synth 8-638] synthesizing module 'FinishUnit_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131676]
INFO: [Synth 8-256] done synthesizing module 'FinishUnit_1' (147#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131676]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkNetworkPort_1' (148#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:131827]
INFO: [Synth 8-638] synthesizing module 'ManagerTileLinkNetworkPort' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132085]
INFO: [Synth 8-256] done synthesizing module 'ManagerTileLinkNetworkPort' (149#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132085]
INFO: [Synth 8-638] synthesizing module 'ManagerTileLinkNetworkPort_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132282]
INFO: [Synth 8-256] done synthesizing module 'ManagerTileLinkNetworkPort_1' (150#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132282]
INFO: [Synth 8-638] synthesizing module 'BasicBus' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:133050]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132479]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter' (151#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:132479]
INFO: [Synth 8-256] done synthesizing module 'BasicBus' (152#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:133050]
INFO: [Synth 8-638] synthesizing module 'BasicBus_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134061]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:133543]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_1' (153#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:133543]
INFO: [Synth 8-256] done synthesizing module 'BasicBus_1' (154#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134061]
INFO: [Synth 8-638] synthesizing module 'BasicBus_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134784]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134512]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_2' (155#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134512]
INFO: [Synth 8-256] done synthesizing module 'BasicBus_2' (156#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:134784]
INFO: [Synth 8-638] synthesizing module 'BasicBus_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:135585]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:135067]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_3' (157#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:135067]
INFO: [Synth 8-256] done synthesizing module 'BasicBus_3' (158#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:135585]
INFO: [Synth 8-638] synthesizing module 'BasicBus_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136273]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136036]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_4' (159#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136036]
INFO: [Synth 8-256] done synthesizing module 'BasicBus_4' (160#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136273]
INFO: [Synth 8-256] done synthesizing module 'PortedTileLinkCrossbar' (161#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:136514]
INFO: [Synth 8-638] synthesizing module 'L2BroadcastHub' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158908]
INFO: [Synth 8-638] synthesizing module 'BufferedBroadcastVoluntaryReleaseTracker' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:140804]
INFO: [Synth 8-256] done synthesizing module 'BufferedBroadcastVoluntaryReleaseTracker' (162#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:140804]
INFO: [Synth 8-638] synthesizing module 'BufferedBroadcastAcquireTracker' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:142134]
INFO: [Synth 8-638] synthesizing module 'Queue_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:141903]
INFO: [Synth 8-256] done synthesizing module 'Queue_4' (163#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:141903]
INFO: [Synth 8-256] done synthesizing module 'BufferedBroadcastAcquireTracker' (164#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:142134]
INFO: [Synth 8-638] synthesizing module 'BufferedBroadcastAcquireTracker_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:145742]
INFO: [Synth 8-256] done synthesizing module 'BufferedBroadcastAcquireTracker_1' (165#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:145742]
INFO: [Synth 8-638] synthesizing module 'BufferedBroadcastAcquireTracker_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:149350]
INFO: [Synth 8-256] done synthesizing module 'BufferedBroadcastAcquireTracker_2' (166#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:149350]
INFO: [Synth 8-638] synthesizing module 'BufferedBroadcastAcquireTracker_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:152958]
INFO: [Synth 8-256] done synthesizing module 'BufferedBroadcastAcquireTracker_3' (167#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:152958]
INFO: [Synth 8-638] synthesizing module 'ClientTileLinkIOArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:157451]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_5' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:156566]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_5' (168#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:156566]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_6' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:157031]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_6' (169#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:157031]
INFO: [Synth 8-256] done synthesizing module 'ClientTileLinkIOArbiter' (170#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:157451]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_7' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158165]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_7' (171#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158165]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_8' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158441]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_8' (172#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158441]
INFO: [Synth 8-256] done synthesizing module 'L2BroadcastHub' (173#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:158908]
INFO: [Synth 8-638] synthesizing module 'MMIOTileLinkManager' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161130]
INFO: [Synth 8-256] done synthesizing module 'MMIOTileLinkManager' (174#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161130]
INFO: [Synth 8-638] synthesizing module 'TileLinkMemoryInterconnect' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161710]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIOArbiter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161654]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIOArbiter_1' (175#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161654]
INFO: [Synth 8-256] done synthesizing module 'TileLinkMemoryInterconnect' (176#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161710]
INFO: [Synth 8-638] synthesizing module 'ClientTileLinkEnqueuer' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161861]
INFO: [Synth 8-256] done synthesizing module 'ClientTileLinkEnqueuer' (177#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161861]
INFO: [Synth 8-638] synthesizing module 'ClientTileLinkIOUnwrapper' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:162653]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_9' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161968]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_9' (178#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:161968]
INFO: [Synth 8-638] synthesizing module 'ReorderQueue' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:162269]
INFO: [Synth 8-256] done synthesizing module 'ReorderQueue' (179#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:162269]
INFO: [Synth 8-256] done synthesizing module 'ClientTileLinkIOUnwrapper' (180#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:162653]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkEnqueuer' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163550]
INFO: [Synth 8-638] synthesizing module 'Queue_8' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163109]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_block_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 26, nWords: 1, wSize: 26, memSize: 26
AWrite Node size: 26, nWords: 1, wSize: 26, memSize: 26
RAM "ram_addr_block_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_client_xact_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_client_xact_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_beat_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_addr_beat_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_is_builtin_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_is_builtin_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_a_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_a_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_union_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 11, nWords: 1, wSize: 11, memSize: 11
AWrite Node size: 11, nWords: 1, wSize: 11, memSize: 11
RAM "ram_union_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_data_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 64, nWords: 1, wSize: 64, memSize: 64
AWrite Node size: 64, nWords: 1, wSize: 64, memSize: 64
RAM "ram_data_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_8' (181#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163109]
INFO: [Synth 8-638] synthesizing module 'Queue_9' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163342]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_beat_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_addr_beat_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_client_xact_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_client_xact_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_manager_xact_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_manager_xact_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_is_builtin_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_is_builtin_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_g_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_g_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_data_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 64, nWords: 1, wSize: 64, memSize: 64
AWrite Node size: 64, nWords: 1, wSize: 64, memSize: 64
RAM "ram_data_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_9' (182#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163342]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkEnqueuer' (183#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163550]
INFO: [Synth 8-638] synthesizing module 'TileLinkRecursiveInterconnect' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165105]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIOCrossbar' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164223]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIORouter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163976]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_10' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163711]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_10' (184#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163711]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIORouter' (185#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:163976]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIOCrossbar' (186#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164223]
INFO: [Synth 8-638] synthesizing module 'TileLinkRecursiveInterconnect_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164888]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIOCrossbar_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164671]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIORouter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164440]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIORouter_1' (187#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164440]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIOCrossbar_1' (188#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164671]
INFO: [Synth 8-256] done synthesizing module 'TileLinkRecursiveInterconnect_1' (189#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:164888]
INFO: [Synth 8-256] done synthesizing module 'TileLinkRecursiveInterconnect' (190#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165105]
INFO: [Synth 8-638] synthesizing module 'PLIC' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165483]
INFO: [Synth 8-4471] merging register '_T_597_reg[1:0]' into '_T_589_reg[1:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165647]
INFO: [Synth 8-256] done synthesizing module 'PLIC' (191#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165483]
INFO: [Synth 8-638] synthesizing module 'DebugModule' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165779]
INFO: [Synth 8-256] done synthesizing module 'DebugModule' (192#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:165779]
INFO: [Synth 8-638] synthesizing module 'ClientTileLinkEnqueuer_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168174]
INFO: [Synth 8-638] synthesizing module 'Queue_11' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167296]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_block_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 26, nWords: 1, wSize: 26, memSize: 26
AWrite Node size: 26, nWords: 1, wSize: 26, memSize: 26
RAM "ram_addr_block_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_client_xact_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_client_xact_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_beat_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_addr_beat_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_is_builtin_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_is_builtin_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_a_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_a_type_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_union_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 11, nWords: 1, wSize: 11, memSize: 11
AWrite Node size: 11, nWords: 1, wSize: 11, memSize: 11
RAM "ram_union_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_data_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 64, nWords: 1, wSize: 64, memSize: 64
AWrite Node size: 64, nWords: 1, wSize: 64, memSize: 64
RAM "ram_data_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_11' (193#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167296]
INFO: [Synth 8-638] synthesizing module 'Queue_12' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167529]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_block_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 26, nWords: 1, wSize: 26, memSize: 26
AWrite Node size: 26, nWords: 1, wSize: 26, memSize: 26
RAM "ram_addr_block_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_p_type_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_p_type_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_12' (194#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167529]
INFO: [Synth 8-638] synthesizing module 'Queue_13' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167637]
INFO: [Synth 8-256] done synthesizing module 'Queue_13' (195#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167637]
INFO: [Synth 8-638] synthesizing module 'Queue_14' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167893]
INFO: [Synth 8-256] done synthesizing module 'Queue_14' (196#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:167893]
INFO: [Synth 8-256] done synthesizing module 'ClientTileLinkEnqueuer_1' (197#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168174]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkEnqueuer_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168727]
INFO: [Synth 8-638] synthesizing module 'Queue_16' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168471]
INFO: [Synth 8-256] done synthesizing module 'Queue_16' (198#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168471]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkEnqueuer_1' (199#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168727]
INFO: [Synth 8-256] done synthesizing module 'DefaultCoreplex' (200#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:168888]
INFO: [Synth 8-638] synthesizing module 'TileLinkRecursiveInterconnect_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171477]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIOCrossbar_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171328]
INFO: [Synth 8-638] synthesizing module 'ClientUncachedTileLinkIORouter_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171152]
INFO: [Synth 8-638] synthesizing module 'LockingRRArbiter_12' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171044]
INFO: [Synth 8-256] done synthesizing module 'LockingRRArbiter_12' (201#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171044]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIORouter_2' (202#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171152]
INFO: [Synth 8-256] done synthesizing module 'ClientUncachedTileLinkIOCrossbar_2' (203#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171328]
INFO: [Synth 8-256] done synthesizing module 'TileLinkRecursiveInterconnect_2' (204#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171477]
INFO: [Synth 8-638] synthesizing module 'NastiIOTileLinkIOConverter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172332]
INFO: [Synth 8-638] synthesizing module 'ReorderQueue_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171626]
INFO: [Synth 8-256] done synthesizing module 'ReorderQueue_2' (205#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:171626]
INFO: [Synth 8-638] synthesizing module 'IdMapper' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172035]
INFO: [Synth 8-256] done synthesizing module 'IdMapper' (206#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172035]
INFO: [Synth 8-638] synthesizing module 'LockingArbiter_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172052]
INFO: [Synth 8-256] done synthesizing module 'LockingArbiter_2' (207#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172052]
INFO: [Synth 8-256] done synthesizing module 'NastiIOTileLinkIOConverter' (208#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:172332]
INFO: [Synth 8-638] synthesizing module 'Queue_17' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173285]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 32, nWords: 1, wSize: 32, memSize: 32
AWrite Node size: 32, nWords: 1, wSize: 32, memSize: 32
RAM "ram_addr_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_len_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 8, nWords: 1, wSize: 8, memSize: 8
AWrite Node size: 8, nWords: 1, wSize: 8, memSize: 8
RAM "ram_len_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_size_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_size_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_burst_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_burst_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_lock_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_lock_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_cache_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_cache_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_prot_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_prot_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_qos_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_qos_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_region_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_region_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 5, nWords: 1, wSize: 5, memSize: 5
AWrite Node size: 5, nWords: 1, wSize: 5, memSize: 5
RAM "ram_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_user_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_user_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_17' (209#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173285]
INFO: [Synth 8-638] synthesizing module 'Queue_19' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173618]
INFO: [Synth 8-256] done synthesizing module 'Queue_19' (210#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173618]
INFO: [Synth 8-638] synthesizing module 'Queue_20' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173849]
INFO: [Synth 8-256] done synthesizing module 'Queue_20' (211#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:173849]
INFO: [Synth 8-638] synthesizing module 'Queue_21' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:174080]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_resp_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_resp_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 5, nWords: 1, wSize: 5, memSize: 5
AWrite Node size: 5, nWords: 1, wSize: 5, memSize: 5
RAM "ram_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_user_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_user_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_21' (212#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:174080]
INFO: [Synth 8-638] synthesizing module 'SerialAdapter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:174213]
INFO: [Synth 8-256] done synthesizing module 'SerialAdapter' (213#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:174213]
INFO: [Synth 8-638] synthesizing module 'Queue_22' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:175367]
INFO: [Synth 8-256] done synthesizing module 'Queue_22' (214#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:175367]
INFO: [Synth 8-256] done synthesizing module 'FPGAZynqTop' (215#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:175498]
INFO: [Synth 8-638] synthesizing module 'ZynqAXISlave' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185829]
INFO: [Synth 8-638] synthesizing module 'NastiCrossbar' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:184440]
INFO: [Synth 8-638] synthesizing module 'NastiRouter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183815]
INFO: [Synth 8-638] synthesizing module 'NastiErrorSlave' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183092]
INFO: [Synth 8-638] synthesizing module 'Queue_24' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:182676]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_addr_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 32, nWords: 1, wSize: 32, memSize: 32
AWrite Node size: 32, nWords: 1, wSize: 32, memSize: 32
RAM "ram_addr_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_len_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 8, nWords: 1, wSize: 8, memSize: 8
AWrite Node size: 8, nWords: 1, wSize: 8, memSize: 8
RAM "ram_len_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_size_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_size_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_burst_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 2, nWords: 1, wSize: 2, memSize: 2
AWrite Node size: 2, nWords: 1, wSize: 2, memSize: 2
RAM "ram_burst_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_lock_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_lock_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_cache_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_cache_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_prot_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 3, nWords: 1, wSize: 3, memSize: 3
AWrite Node size: 3, nWords: 1, wSize: 3, memSize: 3
RAM "ram_prot_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_qos_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_qos_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_region_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 4, nWords: 1, wSize: 4, memSize: 4
AWrite Node size: 4, nWords: 1, wSize: 4, memSize: 4
RAM "ram_region_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_id_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 12, nWords: 1, wSize: 12, memSize: 12
AWrite Node size: 12, nWords: 1, wSize: 12, memSize: 12
RAM "ram_id_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_user_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 1, nWords: 1, wSize: 1, memSize: 1
AWrite Node size: 1, nWords: 1, wSize: 1, memSize: 1
RAM "ram_user_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_24' (216#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:182676]
INFO: [Synth 8-638] synthesizing module 'Queue_25' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183009]
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
ARead Node size: 12, nWords: 1, wSize: 12, memSize: 12
AWrite Node size: 12, nWords: 1, wSize: 12, memSize: 12
RAM "ram_reg" dissolved into registers
INFO: [Synth 8-256] done synthesizing module 'Queue_25' (217#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183009]
INFO: [Synth 8-256] done synthesizing module 'NastiErrorSlave' (218#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183092]
INFO: [Synth 8-638] synthesizing module 'RRArbiter_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183416]
INFO: [Synth 8-256] done synthesizing module 'RRArbiter_1' (219#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183416]
INFO: [Synth 8-638] synthesizing module 'HellaPeekingArbiter' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183577]
INFO: [Synth 8-256] done synthesizing module 'HellaPeekingArbiter' (220#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183577]
INFO: [Synth 8-256] done synthesizing module 'NastiRouter' (221#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:183815]
INFO: [Synth 8-256] done synthesizing module 'NastiCrossbar' (222#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:184440]
INFO: [Synth 8-638] synthesizing module 'NastiFIFO' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185124]
INFO: [Synth 8-638] synthesizing module 'Queue_26' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:184993]
INFO: [Synth 8-256] done synthesizing module 'Queue_26' (223#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:184993]
INFO: [Synth 8-256] done synthesizing module 'NastiFIFO' (224#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185124]
INFO: [Synth 8-638] synthesizing module 'ResetController' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185602]
INFO: [Synth 8-256] done synthesizing module 'ResetController' (225#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185602]
INFO: [Synth 8-256] done synthesizing module 'ZynqAXISlave' (226#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:185829]
INFO: [Synth 8-256] done synthesizing module 'Top' (227#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:186516]
WARNING: [Synth 8-689] width (1) of port connection 'io_ps_axi_slave_r_bits_resp' does not match port width (2) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:301]
WARNING: [Synth 8-689] width (1) of port connection 'io_ps_axi_slave_b_bits_resp' does not match port width (2) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:308]
WARNING: [Synth 8-689] width (6) of port connection 'io_mem_axi_ar_bits_id' does not match port width (5) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:313]
WARNING: [Synth 8-689] width (6) of port connection 'io_mem_axi_aw_bits_id' does not match port width (5) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:325]
WARNING: [Synth 8-689] width (6) of port connection 'io_mem_axi_b_bits_id' does not match port width (5) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:342]
WARNING: [Synth 8-689] width (6) of port connection 'io_mem_axi_r_bits_id' does not match port width (5) of module 'Top' [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:346]
WARNING: [Synth 8-350] instance 'top' of module 'Top' requires 92 connections, but only 78 given [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:264]
INFO: [Synth 8-638] synthesizing module 'IBUFG' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:14569]
Parameter CAPACITANCE bound to: DONT_CARE - type: string
Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
INFO: [Synth 8-256] done synthesizing module 'IBUFG' (228#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:14569]
INFO: [Synth 8-638] synthesizing module 'MMCME2_BASE' [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:20516]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: float
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.000000 - type: float
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-256] done synthesizing module 'MMCME2_BASE' (229#1) [/home/alpha/Xilinx/Vivado/2016.2/scripts/rt/data/unisim_comp.v:20516]
INFO: [Synth 8-256] done synthesizing module 'rocketchip_wrapper' (230#1) [/home/alpha/fpga-zynq/zedboard/src/verilog/rocketchip_wrapper.v:4]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[31]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[30]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[29]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[28]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[27]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[26]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[25]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[24]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[23]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[22]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[21]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[20]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[19]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[18]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[17]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[16]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[15]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[14]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[13]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[12]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[11]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[10]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[9]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[8]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[7]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[6]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[5]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[4]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_addr[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[7]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[6]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[5]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[4]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_len[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_size[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_size[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_size[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_burst[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_burst[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_lock
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_cache[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_cache[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_cache[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_cache[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_prot[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_prot[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_prot[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_qos[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_qos[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_qos[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_qos[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_region[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_region[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_region[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_region[0]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_aw_bits_user
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[31]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[30]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[29]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[28]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[27]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[26]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[25]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[24]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[23]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[22]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[21]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[20]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[19]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[18]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[17]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[16]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[15]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[14]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[13]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[12]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[11]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[10]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[9]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[8]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[7]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[6]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[5]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[4]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[3]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[2]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_data[1]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_last
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[11]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[10]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[9]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[8]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[7]
WARNING: [Synth 8-3331] design ResetController has unconnected port io_nasti_w_bits_id[6]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 1567.445 ; gain = 684.410 ; free physical = 130 ; free virtual = 4341
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin alloc_arb:io_in_0_bits to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105041]
WARNING: [Synth 8-3295] tying undriven pin alloc_arb:io_in_1_bits to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105041]
WARNING: [Synth 8-3295] tying undriven pin mmio_alloc_arb:io_in_0_bits to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105199]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_0_bits_way_en[3] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_0_bits_way_en[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_0_bits_way_en[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_0_bits_way_en[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_4_bits_way_en[3] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_4_bits_way_en[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_4_bits_way_en[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin metaReadArb:io_in_4_bits_way_en[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:108431]
WARNING: [Synth 8-3295] tying undriven pin core:io_rocc_cmd_ready to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:129176]
WARNING: [Synth 8-3295] tying undriven pin core:io_rocc_interrupt to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:129176]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_src[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_src[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_src[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_dst[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_dst[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_header_dst[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[25] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[24] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[23] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[22] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[21] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[20] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[19] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[18] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[17] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[16] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[15] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[14] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[13] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[12] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[11] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[10] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[9] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[8] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[7] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[6] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[5] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[4] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[3] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_block[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_client_xact_id[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_client_xact_id[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_beat[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_beat[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_addr_beat[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_is_builtin_type to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_a_type[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_a_type[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_a_type[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[10] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[9] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[8] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[7] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[6] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[5] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[4] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[3] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[2] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[1] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_union[0] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[63] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[62] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[61] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[60] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[59] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[58] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[57] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[56] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[55] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[54] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[53] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[52] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[51] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[50] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[49] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[48] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[47] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[46] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[45] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[44] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[43] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[42] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[41] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[40] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[39] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[38] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[37] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[36] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[35] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[34] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[33] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[32] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[31] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[30] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
WARNING: [Synth 8-3295] tying undriven pin acqNet:io_in_0_bits_payload_data[29] to constant 0 [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:139100]
INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:56 ; elapsed = 00:01:00 . Memory (MB): peak = 1567.445 ; gain = 684.410 ; free physical = 131 ; free virtual = 4343
---------------------------------------------------------------------------------
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor' instantiated as 'top/FPGAZynqTop/TLMonitor' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:178812]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_1' instantiated as 'top/FPGAZynqTop/TLMonitor_1' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:178940]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_10' instantiated as 'top/FPGAZynqTop/TLMonitor_10' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179931]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_11' instantiated as 'top/FPGAZynqTop/TLMonitor_11' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179975]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_2' instantiated as 'top/FPGAZynqTop/TLMonitor_2' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179068]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_3' instantiated as 'top/FPGAZynqTop/TLMonitor_3' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179112]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_4' instantiated as 'top/FPGAZynqTop/TLMonitor_4' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179240]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_5' instantiated as 'top/FPGAZynqTop/TLMonitor_5' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179368]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_6' instantiated as 'top/FPGAZynqTop/TLMonitor_6' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179412]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_7' instantiated as 'top/FPGAZynqTop/TLMonitor_7' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179584]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_8' instantiated as 'top/FPGAZynqTop/TLMonitor_8' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179628]
WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'TLMonitor_9' instantiated as 'top/FPGAZynqTop/TLMonitor_9' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:179803]
INFO: [Netlist 29-17] Analyzing 15 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7z020clg484-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/system_proc_sys_reset_0_0_board.xdc] for cell 'system_i/proc_sys_reset_0/U0'
Finished Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/system_proc_sys_reset_0_0_board.xdc] for cell 'system_i/proc_sys_reset_0/U0'
Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/system_proc_sys_reset_0_0.xdc] for cell 'system_i/proc_sys_reset_0/U0'
Finished Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_proc_sys_reset_0_0/system_proc_sys_reset_0_0.xdc] for cell 'system_i/proc_sys_reset_0/U0'
Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
Finished Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/rocketchip_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/rocketchip_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/alpha/fpga-zynq/zedboard/src/constrs/base.xdc]
Finished Parsing XDC File [/home/alpha/fpga-zynq/zedboard/src/constrs/base.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/alpha/fpga-zynq/zedboard/src/constrs/base.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/rocketchip_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/rocketchip_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/rocketchip_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/rocketchip_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Completed Processing XDC Constraints
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 14 instances were transformed.
FDR => FDRE: 12 instances
MMCME2_BASE => MMCME2_ADV: 1 instances
SRL16 => SRL16E: 1 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1844.520 ; gain = 0.000 ; free physical = 128 ; free virtual = 4160
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:01:19 ; elapsed = 00:01:29 . Memory (MB): peak = 1844.523 ; gain = 961.488 ; free physical = 142 ; free virtual = 4158
---------------------------------------------------------------------------------
INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 4 processes.
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:19 ; elapsed = 00:01:29 . Memory (MB): peak = 1864.160 ; gain = 981.125 ; free physical = 138 ; free virtual = 4153
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for system_i/proc_sys_reset_0/U0. (constraint file /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/dont_touch.xdc, line 28).
Applied set_property DONT_TOUCH = true for system_i/processing_system7_0/inst. (constraint file /home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.runs/synth_1/dont_touch.xdc, line 36).
Applied set_property DONT_TOUCH = true for system_i. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/axi_interconnect_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/axi_interconnect_0/s00_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/axi_interconnect_1. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/axi_interconnect_1/s00_couplers/auto_pc. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/proc_sys_reset_0. (constraint file auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for system_i/processing_system7_0. (constraint file auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:19 ; elapsed = 00:01:30 . Memory (MB): peak = 1864.160 ; gain = 981.125 ; free physical = 70 ; free virtual = 4067
---------------------------------------------------------------------------------
INFO: [Synth 8-5544] ROM "leaving_empty_fwft" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:823]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:763]
INFO: [Synth 8-5818] HDL ADVISOR - The operator resource <adder> is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v:763]
INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [/home/alpha/fpga-zynq/zedboard/zedboard_rocketchip_ZynqConfig/zedboard_rocketchip_ZynqConfig.srcs/sources_1/bd/system/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd:222]
INFO: [Synth 8-5544] ROM "_T_3030" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1034" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1053" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1083" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1102" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
WARNING: [Synth 8-3936] Found unconnected internal register '_T_1825_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:4833]
INFO: [Synth 8-5544] ROM "_T_1776_0_state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1825_0_lut" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_548" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "buf_data" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-4471] merging register 'reg_mstatus_zero2_reg[1:0]' into 'reg_mstatus_xs_reg[1:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79678]
INFO: [Synth 8-4471] merging register 'reg_mstatus_hpp_reg[1:0]' into 'reg_mstatus_xs_reg[1:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79687]
INFO: [Synth 8-4471] merging register 'reg_mstatus_hpie_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79690]
INFO: [Synth 8-4471] merging register 'reg_mstatus_upie_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79692]
INFO: [Synth 8-4471] merging register 'reg_mstatus_hie_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79694]
INFO: [Synth 8-4471] merging register 'reg_mstatus_uie_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:79696]
INFO: [Synth 8-4471] merging register 'reg_dcsr_ndreset_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80608]
INFO: [Synth 8-4471] merging register 'reg_dcsr_fullreset_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80609]
INFO: [Synth 8-4471] merging register 'reg_dcsr_ebreakh_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80605]
INFO: [Synth 8-4471] merging register 'reg_dcsr_zero2_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80604]
INFO: [Synth 8-4471] merging register 'reg_dcsr_stopcycle_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80601]
INFO: [Synth 8-4471] merging register 'reg_dcsr_stoptime_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80601]
INFO: [Synth 8-4471] merging register 'reg_dcsr_zero1_reg' into 'reg_mstatus_sd_rv32_reg' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:80598]
INFO: [Synth 8-5544] ROM "debugTVec" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_5921" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "reg_mstatus_vm" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_6008" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "reg_dcsr_cause" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "reg_sptbr_ppn" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "count" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_7486" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_7923" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_7224" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ex_ctrl_sel_alu2" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ex_ctrl_mem_cmd" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-4471] merging register 'tag_array_1_tag_rdata_addr_pipe_0_reg[5:0]' into 'tag_array_0_tag_rdata_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91726]
INFO: [Synth 8-4471] merging register 'tag_array_2_tag_rdata_addr_pipe_0_reg[5:0]' into 'tag_array_0_tag_rdata_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91732]
INFO: [Synth 8-4471] merging register 'tag_array_3_tag_rdata_addr_pipe_0_reg[5:0]' into 'tag_array_0_tag_rdata_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91738]
WARNING: [Synth 8-3936] Found unconnected internal register 's1_vaddr_reg' and it is trimmed from '39' to '12' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:91668]
INFO: [Synth 8-5544] ROM "ppns_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_4" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_5" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_6" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_7" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_4" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_5" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_6" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ppns_7" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_271" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_279" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_287" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "idxs_0" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_1" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_2" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_3" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_4" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_5" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_6" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_7" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_8" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_9" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_10" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_11" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_12" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_13" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_14" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_15" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_16" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_17" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_18" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_19" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_20" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_21" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_22" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_23" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_24" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_25" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_26" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_27" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_28" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_29" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_30" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_31" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_32" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_33" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_34" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_35" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_36" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_37" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_38" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idxs_39" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "_T_1124" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2536" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2184" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "meta_hazard" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "meta_hazard" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2536" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2184" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "meta_hazard" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "meta_hazard" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_1611_a_type" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-4471] merging register '_T_2352_1__T_2391_addr_pipe_0_reg[5:0]' into '_T_2352_0__T_2391_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105894]
INFO: [Synth 8-4471] merging register '_T_2352_2__T_2391_addr_pipe_0_reg[5:0]' into '_T_2352_0__T_2391_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105900]
INFO: [Synth 8-4471] merging register '_T_2352_3__T_2391_addr_pipe_0_reg[5:0]' into '_T_2352_0__T_2391_addr_pipe_0_reg[5:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:105906]
WARNING: [Synth 8-3936] Found unconnected internal register 'in_rm_reg' and it is trimmed from '3' to '2' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112060]
WARNING: [Synth 8-3936] Found unconnected internal register 'in_in1_reg' and it is trimmed from '65' to '33' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112062]
WARNING: [Synth 8-3936] Found unconnected internal register 'in_in3_reg' and it is trimmed from '65' to '33' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:112064]
WARNING: [Synth 8-3936] Found unconnected internal register '_T_161_in1_reg' and it is trimmed from '65' to '64' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:115150]
WARNING: [Synth 8-3936] Found unconnected internal register '_T_161_rm_reg' and it is trimmed from '3' to '2' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:115148]
WARNING: [Synth 8-3936] Found unconnected internal register '_T_163_rm_reg' and it is trimmed from '3' to '2' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116600]
WARNING: [Synth 8-3936] Found unconnected internal register 'in_rm_reg' and it is trimmed from '3' to '2' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:119312]
WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:124012]
WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '22' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:124007]
WARNING: [Synth 8-3936] Found unconnected internal register 'r_req_prv_reg' and it is trimmed from '2' to '1' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:126838]
INFO: [Synth 8-5544] ROM "_T_2431_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_4" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_5" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_6" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_7" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_4" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_5" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_6" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2431_7" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "_T_2693" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "state0" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_4" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_5" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_6" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_7" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_1" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_2" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "data_buffer_3" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Common 17-14] Message 'Synth 8-5544' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4471] merging register 'CONTROLReg_serial_reg[2:0]' into 'CONTROLReg_buserror_reg[2:0]' [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:166406]
WARNING: [Synth 8-3936] Found unconnected internal register 'sbAcqReg_addr_block_reg' and it is trimmed from '26' to '6' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:166804]
---------------------------------------------------------------------------------
Finished
from fpga-zynq.
ninode
commented on May 18, 2024
log3:
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:46 ; elapsed = 00:02:27 . Memory (MB): peak = 1864.160 ; gain = 981.125 ; free physical = 73 ; free virtual = 2893
---------------------------------------------------------------------------------
Report RTL Partitions:
+------+------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+------------------------+------------+----------+
|1 |FPU__GB0 | 1| 34460|
|2 |FPU__GB1 | 1| 34686|
|3 |RocketTile__GCB0 | 1| 29182|
|4 |HellaCache | 1| 13892|
|5 |RocketTile__GCB2 | 1| 13988|
|6 |L2BroadcastHub | 1| 43943|
|7 |DefaultCoreplex__GCB1 | 1| 6878|
|8 |FPGAZynqTop__GC0 | 1| 13352|
|9 |ZynqAXISlave | 1| 857|
|10 |rocketchip_wrapper__GC0 | 1| 2309|
+------+------------------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 107 Bit Adders := 1
2 Input 105 Bit Adders := 1
2 Input 73 Bit Adders := 1
3 Input 65 Bit Adders := 1
2 Input 64 Bit Adders := 8
3 Input 64 Bit Adders := 2
2 Input 58 Bit Adders := 2
2 Input 55 Bit Adders := 2
2 Input 54 Bit Adders := 3
2 Input 49 Bit Adders := 1
2 Input 40 Bit Adders := 3
2 Input 39 Bit Adders := 1
2 Input 32 Bit Adders := 3
2 Input 29 Bit Adders := 1
2 Input 26 Bit Adders := 4
2 Input 25 Bit Adders := 1
2 Input 21 Bit Adders := 1
2 Input 20 Bit Adders := 1
2 Input 14 Bit Adders := 3
4 Input 14 Bit Adders := 1
3 Input 14 Bit Adders := 2
3 Input 13 Bit Adders := 2
2 Input 13 Bit Adders := 2
2 Input 12 Bit Adders := 5
4 Input 11 Bit Adders := 1
3 Input 11 Bit Adders := 2
2 Input 11 Bit Adders := 3
3 Input 10 Bit Adders := 2
2 Input 9 Bit Adders := 2
2 Input 8 Bit Adders := 5
14 Input 8 Bit Adders := 1
2 Input 7 Bit Adders := 9
2 Input 6 Bit Adders := 7
3 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 12
16 Input 5 Bit Adders := 2
2 Input 4 Bit Adders := 21
3 Input 4 Bit Adders := 6
8 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 94
3 Input 3 Bit Adders := 3
4 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 11
3 Input 2 Bit Adders := 3
4 Input 2 Bit Adders := 3
4 Input 1 Bit Adders := 1
3 Input 1 Bit Adders := 16
2 Input 1 Bit Adders := 59
+---XORs :
2 Input 108 Bit XORs := 1
2 Input 65 Bit XORs := 1
2 Input 64 Bit XORs := 3
2 Input 50 Bit XORs := 1
2 Input 26 Bit XORs := 2
2 Input 12 Bit XORs := 2
2 Input 9 Bit XORs := 2
2 Input 7 Bit XORs := 2
2 Input 2 Bit XORs := 1
4 Input 1 Bit XORs := 2
2 Input 1 Bit XORs := 81
3 Input 1 Bit XORs := 2
+---Registers :
256 Bit Registers := 1
130 Bit Registers := 1
105 Bit Registers := 1
65 Bit Registers := 50
64 Bit Registers := 86
62 Bit Registers := 2
58 Bit Registers := 4
54 Bit Registers := 4
53 Bit Registers := 1
51 Bit Registers := 4
40 Bit Registers := 19
39 Bit Registers := 11
38 Bit Registers := 2
34 Bit Registers := 20
33 Bit Registers := 3
32 Bit Registers := 41
31 Bit Registers := 2
27 Bit Registers := 7
26 Bit Registers := 15
22 Bit Registers := 1
21 Bit Registers := 1
20 Bit Registers := 30
17 Bit Registers := 2
16 Bit Registers := 5
14 Bit Registers := 3
13 Bit Registers := 1
12 Bit Registers := 11
11 Bit Registers := 85
10 Bit Registers := 5
9 Bit Registers := 7
8 Bit Registers := 81
7 Bit Registers := 12
6 Bit Registers := 29
5 Bit Registers := 56
4 Bit Registers := 51
3 Bit Registers := 250
2 Bit Registers := 118
1 Bit Registers := 558
+---Multipliers :
53x53 Multipliers := 1
54x54 Multipliers := 1
9x65 Multipliers := 1
+---RAMs :
32K Bit RAMs := 8
1K Bit RAMs := 10
640 Bit RAMs := 2
512 Bit RAMs := 3
256 Bit RAMs := 1
128 Bit RAMs := 7
112 Bit RAMs := 2
80 Bit RAMs := 4
64 Bit RAMs := 2
52 Bit RAMs := 2
48 Bit RAMs := 2
24 Bit RAMs := 1
16 Bit RAMs := 4
10 Bit RAMs := 2
8 Bit RAMs := 5
6 Bit RAMs := 22
4 Bit RAMs := 15
2 Bit RAMs := 16
+---Muxes :
2 Input 2080 Bit Muxes := 1
2 Input 130 Bit Muxes := 3
2 Input 129 Bit Muxes := 1
2 Input 109 Bit Muxes := 2
2 Input 105 Bit Muxes := 2
2 Input 104 Bit Muxes := 1
2 Input 95 Bit Muxes := 3
2 Input 88 Bit Muxes := 6
2 Input 87 Bit Muxes := 9
2 Input 79 Bit Muxes := 2
2 Input 66 Bit Muxes := 1
2 Input 65 Bit Muxes := 93
3 Input 64 Bit Muxes := 2
2 Input 64 Bit Muxes := 276
4 Input 64 Bit Muxes := 4
5 Input 64 Bit Muxes := 3
8 Input 64 Bit Muxes := 1
13 Input 64 Bit Muxes := 1
2 Input 60 Bit Muxes := 1
2 Input 59 Bit Muxes := 2
2 Input 58 Bit Muxes := 6
2 Input 56 Bit Muxes := 4
2 Input 55 Bit Muxes := 3
2 Input 54 Bit Muxes := 8
2 Input 53 Bit Muxes := 10
2 Input 52 Bit Muxes := 7
3 Input 52 Bit Muxes := 2
2 Input 51 Bit Muxes := 2
2 Input 50 Bit Muxes := 8
2 Input 48 Bit Muxes := 2
2 Input 46 Bit Muxes := 5
2 Input 45 Bit Muxes := 1
2 Input 43 Bit Muxes := 5
2 Input 42 Bit Muxes := 8
2 Input 40 Bit Muxes := 43
2 Input 39 Bit Muxes := 8
3 Input 38 Bit Muxes := 1
2 Input 38 Bit Muxes := 7
2 Input 34 Bit Muxes := 5
2 Input 33 Bit Muxes := 4
2 Input 32 Bit Muxes := 57
1019 Input 32 Bit Muxes := 1
3 Input 32 Bit Muxes := 1
4 Input 32 Bit Muxes := 1
8 Input 32 Bit Muxes := 2
2 Input 31 Bit Muxes := 1
2 Input 30 Bit Muxes := 4
2 Input 29 Bit Muxes := 7
2 Input 28 Bit Muxes := 4
2 Input 27 Bit Muxes := 9
3 Input 26 Bit Muxes := 1
2 Input 26 Bit Muxes := 26
10 Input 26 Bit Muxes := 1
6 Input 26 Bit Muxes := 1
2 Input 25 Bit Muxes := 13
2 Input 24 Bit Muxes := 3
3 Input 23 Bit Muxes := 3
2 Input 23 Bit Muxes := 7
2 Input 22 Bit Muxes := 6
2 Input 21 Bit Muxes := 4
2 Input 20 Bit Muxes := 36
18 Input 17 Bit Muxes := 1
2 Input 17 Bit Muxes := 1
2 Input 16 Bit Muxes := 4
3 Input 16 Bit Muxes := 2
2 Input 15 Bit Muxes := 1
2 Input 14 Bit Muxes := 7
2 Input 13 Bit Muxes := 7
2 Input 12 Bit Muxes := 21
3 Input 12 Bit Muxes := 2
8 Input 12 Bit Muxes := 2
3 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 74
2 Input 10 Bit Muxes := 9
2 Input 9 Bit Muxes := 29
2 Input 8 Bit Muxes := 226
10 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 19
4 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 60
64 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 97
16 Input 5 Bit Muxes := 1
6 Input 5 Bit Muxes := 3
5 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 138
8 Input 4 Bit Muxes := 3
3 Input 4 Bit Muxes := 2
5 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
6 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 262
3 Input 3 Bit Muxes := 14
8 Input 3 Bit Muxes := 2
5 Input 3 Bit Muxes := 7
4 Input 3 Bit Muxes := 4
9 Input 3 Bit Muxes := 3
7 Input 3 Bit Muxes := 6
10 Input 3 Bit Muxes := 27
2 Input 2 Bit Muxes := 563
3 Input 2 Bit Muxes := 25
4 Input 2 Bit Muxes := 10
5 Input 2 Bit Muxes := 8
9 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 1033
3 Input 1 Bit Muxes := 10
8 Input 1 Bit Muxes := 2
5 Input 1 Bit Muxes := 4
6 Input 1 Bit Muxes := 5
4 Input 1 Bit Muxes := 6
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module WritebackUnit
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
3 Input 4 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---Registers :
26 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 4
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module ProbeUnit
Detailed RTL Component Info :
+---Registers :
26 Bit Registers := 1
4 Bit Registers := 2
2 Bit Registers := 2
+---Muxes :
2 Input 4 Bit Muxes := 4
8 Input 4 Bit Muxes := 1
3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 8
Module Arbiter
Detailed RTL Component Info :
+---Muxes :
2 Input 20 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
Module Arbiter_1__1
Detailed RTL Component Info :
+---Muxes :
2 Input 20 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
Module LockingArbiter
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
2 Bit Registers := 1
+---Muxes :
3 Input 64 Bit Muxes := 1
3 Input 26 Bit Muxes := 1
3 Input 11 Bit Muxes := 1
3 Input 3 Bit Muxes := 2
4 Input 2 Bit Muxes := 4
3 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 2
2 Input 1 Bit Muxes := 3
Module Arbiter_2
Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module Arbiter_3__1
Detailed RTL Component Info :
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module Arbiter_4
Detailed RTL Component Info :
+---Muxes :
2 Input 40 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module Arbiter_5
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
Module Queue_2
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 3
3 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 1
+---RAMs :
640 Bit RAMs := 1
112 Bit RAMs := 1
80 Bit RAMs := 2
48 Bit RAMs := 1
16 Bit RAMs := 1
Module FinishQueue
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
Module MSHR
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
40 Bit Registers := 1
20 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 2
8 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 9
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
8 Input 1 Bit Muxes := 1
Module Queue_2__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 3
3 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 1
+---RAMs :
640 Bit RAMs := 1
112 Bit RAMs := 1
80 Bit RAMs := 2
48 Bit RAMs := 1
16 Bit RAMs := 1
Module FinishQueue__2
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
Module MSHR_1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 1
+---Registers :
40 Bit Registers := 1
20 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 1
+---Muxes :
2 Input 5 Bit Muxes := 2
8 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 6
2 Input 2 Bit Muxes := 9
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
8 Input 1 Bit Muxes := 1
Module FinishQueue__1
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
Module IOMSHR
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 2
40 Bit Registers := 1
7 Bit Registers := 1
5 Bit Registers := 1
3 Bit Registers := 2
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 2
2 Input 56 Bit Muxes := 1
2 Input 48 Bit Muxes := 1
2 Input 32 Bit Muxes := 2
2 Input 16 Bit Muxes := 1
2 Input 11 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 7
2 Input 2 Bit Muxes := 4
3 Input 2 Bit Muxes := 1
Module MSHRFile
Detailed RTL Component Info :
+---Registers :
17 Bit Registers := 1
5 Bit Registers := 1
+---RAMs :
1K Bit RAMs := 1
+---Muxes :
2 Input 20 Bit Muxes := 2
18 Input 17 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
16 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module TLB__1
Detailed RTL Component Info :
+---Registers :
34 Bit Registers := 9
20 Bit Registers := 8
8 Bit Registers := 9
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 20 Bit Muxes := 10
2 Input 9 Bit Muxes := 1
2 Input 8 Bit Muxes := 13
8 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 15
Module MetadataArray
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
6 Bit Registers := 4
+---RAMs :
1K Bit RAMs := 4
+---Muxes :
2 Input 20 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
Module Arbiter_8
Detailed RTL Component Info :
+---Muxes :
5 Input 3 Bit Muxes := 1
Module Arbiter_1
Detailed RTL Component Info :
+---Muxes :
2 Input 20 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
Module DataArray
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 4
+---RAMs :
32K Bit RAMs := 4
Module Arbiter_10
Detailed RTL Component Info :
+---Muxes :
2 Input 12 Bit Muxes := 3
2 Input 4 Bit Muxes := 3
4 Input 2 Bit Muxes := 1
Module Arbiter_11
Detailed RTL Component Info :
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module AMOALU
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
+---XORs :
2 Input 64 Bit XORs := 2
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 9
Module LockingArbiter_1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 6
Module Arbiter_3
Detailed RTL Component Info :
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module HellaCache
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---XORs :
4 Input 1 Bit XORs := 1
+---Registers :
64 Bit Registers := 9
40 Bit Registers := 1
34 Bit Registers := 1
32 Bit Registers := 3
20 Bit Registers := 4
16 Bit Registers := 1
7 Bit Registers := 2
5 Bit Registers := 5
4 Bit Registers := 2
3 Bit Registers := 2
2 Bit Registers := 9
1 Bit Registers := 15
+---Muxes :
2 Input 64 Bit Muxes := 13
2 Input 56 Bit Muxes := 1
2 Input 48 Bit Muxes := 1
2 Input 40 Bit Muxes := 1
2 Input 32 Bit Muxes := 2
2 Input 22 Bit Muxes := 4
2 Input 16 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 3
2 Input 5 Bit Muxes := 3
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 6
2 Input 1 Bit Muxes := 10
5 Input 1 Bit Muxes := 2
Module MulAddRecFN_preMul
Detailed RTL Component Info :
+---Adders :
4 Input 11 Bit Adders := 1
3 Input 11 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 3
3 Input 1 Bit XORs := 1
+---Muxes :
2 Input 24 Bit Muxes := 2
2 Input 11 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
Module MulAddRecFN_postMul
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 2
3 Input 11 Bit Adders := 1
3 Input 10 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---XORs :
2 Input 50 Bit XORs := 1
2 Input 1 Bit XORs := 2
+---Muxes :
2 Input 43 Bit Muxes := 5
2 Input 42 Bit Muxes := 8
2 Input 26 Bit Muxes := 3
2 Input 25 Bit Muxes := 3
3 Input 23 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 21 Bit Muxes := 1
2 Input 10 Bit Muxes := 3
2 Input 9 Bit Muxes := 4
2 Input 8 Bit Muxes := 2
2 Input 7 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 3
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 30
2 Input 1 Bit Muxes := 8
Module MulAddRecFN
Detailed RTL Component Info :
+---Adders :
2 Input 49 Bit Adders := 1
Module FPUFMAPipe
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
65 Bit Registers := 3
33 Bit Registers := 2
5 Bit Registers := 2
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 33 Bit Muxes := 1
Module RecFNToIN
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Muxes :
2 Input 32 Bit Muxes := 2
2 Input 5 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module RecFNToIN_1
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Muxes :
2 Input 64 Bit Muxes := 2
2 Input 6 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module FPToInt
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 2
2 Input 11 Bit Adders := 1
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
65 Bit Registers := 3
5 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 17
+---Muxes :
2 Input 65 Bit Muxes := 2
2 Input 64 Bit Muxes := 6
2 Input 52 Bit Muxes := 2
2 Input 23 Bit Muxes := 2
2 Input 12 Bit Muxes := 2
2 Input 11 Bit Muxes := 1
2 Input 10 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 5 Bit Muxes := 3
Module INToRecFN
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
2 Input 25 Bit Adders := 1
2 Input 7 Bit Adders := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 40
Module INToRecFN_1
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
2 Input 54 Bit Adders := 1
2 Input 7 Bit Adders := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 40
Module IntToFP
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 9 Bit Adders := 1
+---XORs :
2 Input 12 Bit XORs := 1
2 Input 9 Bit XORs := 1
+---Registers :
65 Bit Registers := 1
64 Bit Registers := 1
5 Bit Registers := 2
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 65 Bit Muxes := 3
2 Input 64 Bit Muxes := 1
2 Input 52 Bit Muxes := 1
2 Input 33 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 1
2 Input 5 Bit Muxes := 3
2 Input 4 Bit Muxes := 3
2 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 62
Module RoundRawFNToRecFN__1
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 11 Bit Adders := 1
+---Muxes :
2 Input 26 Bit Muxes := 2
2 Input 25 Bit Muxes := 2
3 Input 23 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 22 Bit Muxes := 1
2 Input 9 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
Module RecFNToRecFN__1
Detailed RTL Component Info :
+---Adders :
2 Input 14 Bit Adders := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module RecFNToRecFN_1
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
+---Muxes :
2 Input 52 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
Module FPToFP
Detailed RTL Component Info :
+---XORs :
2 Input 65 Bit XORs := 1
+---Registers :
65 Bit Registers := 3
5 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 3
+---Muxes :
2 Input 65 Bit Muxes := 8
2 Input 5 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
Module MulAddRecFN_preMul_1
Detailed RTL Component Info :
+---Adders :
4 Input 14 Bit Adders := 1
3 Input 14 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 3
3 Input 1 Bit XORs := 1
+---Muxes :
2 Input 53 Bit Muxes := 2
2 Input 33 Bit Muxes := 1
2 Input 20 Bit Muxes := 1
2 Input 14 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
Module MulAddRecFN_postMul_1
Detailed RTL Component Info :
+---Adders :
2 Input 55 Bit Adders := 2
3 Input 14 Bit Adders := 1
3 Input 13 Bit Adders := 2
2 Input 8 Bit Adders := 1
2 Input 6 Bit Adders := 1
+---XORs :
2 Input 108 Bit XORs := 1
2 Input 1 Bit XORs := 2
+---Muxes :
2 Input 88 Bit Muxes := 6
2 Input 87 Bit Muxes := 9
2 Input 55 Bit Muxes := 3
2 Input 54 Bit Muxes := 3
3 Input 52 Bit Muxes := 1
2 Input 52 Bit Muxes := 1
2 Input 50 Bit Muxes := 4
2 Input 13 Bit Muxes := 3
2 Input 12 Bit Muxes := 4
2 Input 11 Bit Muxes := 2
2 Input 10 Bit Muxes := 2
2 Input 8 Bit Muxes := 2
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 7
2 Input 3 Bit Muxes := 7
2 Input 2 Bit Muxes := 67
2 Input 1 Bit Muxes := 9
Module MulAddRecFN_1
Detailed RTL Component Info :
+---Adders :
2 Input 107 Bit Adders := 1
+---Multipliers :
53x53 Multipliers := 1
Module FPUFMAPipe_1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
65 Bit Registers := 6
5 Bit Registers := 3
2 Bit Registers := 2
1 Bit Registers := 4
+---Muxes :
2 Input 65 Bit Muxes := 1
Module DivSqrtRecF64_mulAddZ31
Detailed RTL Component Info :
+---Adders :
2 Input 54 Bit Adders := 2
2 Input 21 Bit Adders := 1
2 Input 20 Bit Adders := 1
2 Input 14 Bit Adders := 1
2 Input 13 Bit Adders := 2
2 Input 7 Bit Adders := 1
2 Input 4 Bit Adders := 1
2 Input 3 Bit Adders := 3
+---XORs :
2 Input 2 Bit XORs := 1
2 Input 1 Bit XORs := 3
+---Registers :
58 Bit Registers := 2
53 Bit Registers := 1
51 Bit Registers := 4
33 Bit Registers := 1
32 Bit Registers := 1
31 Bit Registers := 1
21 Bit Registers := 1
17 Bit Registers := 1
14 Bit Registers := 3
10 Bit Registers := 1
9 Bit Registers := 3
4 Bit Registers := 1
3 Bit Registers := 9
2 Bit Registers := 3
1 Bit Registers := 21
+---Muxes :
2 Input 105 Bit Muxes := 2
2 Input 104 Bit Muxes := 1
2 Input 56 Bit Muxes := 1
2 Input 54 Bit Muxes := 5
2 Input 53 Bit Muxes := 8
3 Input 52 Bit Muxes := 1
2 Input 52 Bit Muxes := 1
2 Input 51 Bit Muxes := 2
2 Input 50 Bit Muxes := 4
2 Input 46 Bit Muxes := 3
2 Input 33 Bit Muxes := 1
2 Input 30 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 25 Bit Muxes := 1
2 Input 24 Bit Muxes := 1
2 Input 21 Bit Muxes := 3
2 Input 20 Bit Muxes := 1
2 Input 17 Bit Muxes := 1
2 Input 15 Bit Muxes := 1
2 Input 14 Bit Muxes := 6
2 Input 13 Bit Muxes := 2
2 Input 12 Bit Muxes := 5
2 Input 11 Bit Muxes := 1
2 Input 10 Bit Muxes := 2
2 Input 9 Bit Muxes := 9
2 Input 4 Bit Muxes := 3
3 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 11
2 Input 2 Bit Muxes := 5
2 Input 1 Bit Muxes := 25
Module Mul54
Detailed RTL Component Info :
+---Adders :
2 Input 105 Bit Adders := 1
+---Registers :
105 Bit Registers := 1
54 Bit Registers := 4
1 Bit Registers := 2
+---Multipliers :
54x54 Multipliers := 1
Module RoundRawFNToRecFN
Detailed RTL Component Info :
+---Adders :
2 Input 26 Bit Adders := 1
2 Input 11 Bit Adders := 1
+---Muxes :
2 Input 26 Bit Muxes := 2
2 Input 25 Bit Muxes := 2
3 Input 23 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 22 Bit Muxes := 1
2 Input 9 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
Module RecFNToRecFN
Detailed RTL Component Info :
+---Adders :
2 Input 14 Bit Adders := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module FPU
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 1
2 Input 9 Bit Adders := 1
+---XORs :
2 Input 12 Bit XORs := 1
2 Input 9 Bit XORs := 1
+---Registers :
65 Bit Registers := 33
64 Bit Registers := 1
22 Bit Registers := 1
12 Bit Registers := 1
5 Bit Registers := 11
3 Bit Registers := 1
2 Bit Registers := 4
1 Bit Registers := 41
+---Muxes :
2 Input 2080 Bit Muxes := 1
2 Input 65 Bit Muxes := 78
2 Input 64 Bit Muxes := 1
2 Input 52 Bit Muxes := 1
2 Input 23 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 9 Bit Muxes := 1
2 Input 5 Bit Muxes := 21
2 Input 4 Bit Muxes := 5
4 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 13
2 Input 2 Bit Muxes := 69
2 Input 1 Bit Muxes := 41
Module RVCExpander
Detailed RTL Component Info :
+---Muxes :
2 Input 32 Bit Muxes := 13
2 Input 31 Bit Muxes := 1
2 Input 30 Bit Muxes := 3
2 Input 29 Bit Muxes := 7
2 Input 28 Bit Muxes := 4
2 Input 25 Bit Muxes := 5
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 35
5 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
Module IBuf
Detailed RTL Component Info :
+---Adders :
2 Input 40 Bit Adders := 1
2 Input 2 Bit Adders := 4
3 Input 2 Bit Adders := 3
4 Input 2 Bit Adders := 3
4 Input 1 Bit Adders := 1
3 Input 1 Bit Adders := 1
+---Registers :
40 Bit Registers := 1
39 Bit Registers := 1
32 Bit Registers := 1
7 Bit Registers := 1
6 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 6
+---Muxes :
2 Input 40 Bit Muxes := 1
2 Input 39 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 10
5 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module CSRFile
Detailed RTL Component Info :
+---Adders :
2 Input 58 Bit Adders := 2
2 Input 7 Bit Adders := 2
+---Registers :
64 Bit Registers := 9
58 Bit Registers := 2
40 Bit Registers := 6
39 Bit Registers := 3
38 Bit Registers := 1
32 Bit Registers := 3
31 Bit Registers := 1
12 Bit Registers := 1
7 Bit Registers := 1
6 Bit Registers := 4
5 Bit Registers := 2
4 Bit Registers := 3
3 Bit Registers := 2
2 Bit Registers := 7
1 Bit Registers := 34
+---Muxes :
2 Input 64 Bit Muxes := 37
2 Input 59 Bit Muxes := 2
2 Input 58 Bit Muxes := 6
2 Input 45 Bit Muxes := 1
2 Input 40 Bit Muxes := 25
2 Input 39 Bit Muxes := 2
3 Input 38 Bit Muxes := 1
2 Input 32 Bit Muxes := 7
2 Input 13 Bit Muxes := 1
2 Input 12 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 5
64 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 7
6 Input 5 Bit Muxes := 1
5 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 17
3 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 76
Module BreakpointUnit
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module ALU
Detailed RTL Component Info :
+---Adders :
3 Input 64 Bit Adders := 1
+---XORs :
2 Input 64 Bit XORs := 1
2 Input 1 Bit XORs := 1
+---Muxes :
2 Input 64 Bit Muxes := 9
2 Input 32 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
Module MulDiv
Detailed RTL Component Info :
+---Adders :
2 Input 73 Bit Adders := 1
3 Input 65 Bit Adders := 1
2 Input 7 Bit Adders := 1
3 Input 6 Bit Adders := 1
+---Registers :
130 Bit Registers := 1
65 Bit Registers := 1
7 Bit Registers := 1
5 Bit Registers := 1
3 Bit Registers := 1
1 Bit Registers := 4
+---Multipliers :
9x65 Multipliers := 1
+---Muxes :
2 Input 130 Bit Muxes := 3
2 Input 129 Bit Muxes := 1
2 Input 65 Bit Muxes := 1
2 Input 64 Bit Muxes := 4
2 Input 32 Bit Muxes := 2
4 Input 7 Bit Muxes := 1
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 4
2 Input 3 Bit Muxes := 26
4 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 82
6 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module Rocket
Detailed RTL Component Info :
+---Adders :
2 Input 40 Bit Adders := 1
2 Input 39 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 1
+---Registers :
64 Bit Registers := 7
62 Bit Registers := 2
40 Bit Registers := 3
39 Bit Registers := 2
32 Bit Registers := 5
7 Bit Registers := 2
6 Bit Registers := 2
5 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 5
2 Bit Registers := 8
1 Bit Registers := 58
+---RAMs :
1K Bit RAMs := 1
+---Muxes :
2 Input 64 Bit Muxes := 16
4 Input 64 Bit Muxes := 2
5 Input 64 Bit Muxes := 1
8 Input 64 Bit Muxes := 1
2 Input 40 Bit Muxes := 4
2 Input 32 Bit Muxes := 11
2 Input 11 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 4
3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
5 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 16
Module HellaCacheArbiter
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 40 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module RRArbiter
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
+---Muxes :
2 Input 27 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 6
Module PTW
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
38 Bit Registers := 1
32 Bit Registers := 8
27 Bit Registers := 1
20 Bit Registers := 8
16 Bit Registers := 1
8 Bit Registers := 2
3 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 15
+---Muxes :
2 Input 38 Bit Muxes := 7
2 Input 20 Bit Muxes := 8
2 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 3
9 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 15
3 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 4
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 43
Module ICache
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---XORs :
4 Input 1 Bit XORs := 1
+---Registers :
256 Bit Registers := 1
64 Bit Registers := 4
32 Bit Registers := 1
16 Bit Registers := 1
12 Bit Registers := 1
6 Bit Registers := 4
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 7
+---RAMs :
32K Bit RAMs := 4
1K Bit RAMs := 4
+---Muxes :
2 Input 64 Bit Muxes := 4
2 Input 12 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module TLB
Detailed RTL Component Info :
+---Registers :
34 Bit Registers := 9
20 Bit Registers := 8
8 Bit Registers := 9
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 20 Bit Muxes := 10
2 Input 9 Bit Muxes := 1
2 Input 8 Bit Muxes := 13
8 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 15
Module BTB
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 3
+---XORs :
2 Input 7 Bit XORs := 2
+---Registers :
40 Bit Registers := 3
39 Bit Registers := 4
27 Bit Registers := 6
11 Bit Registers := 80
7 Bit Registers := 1
6 Bit Registers := 3
3 Bit Registers := 81
2 Bit Registers := 1
1 Bit Registers := 46
+---RAMs :
256 Bit RAMs := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 40 Bit Muxes := 6
2 Input 39 Bit Muxes := 5
2 Input 27 Bit Muxes := 8
2 Input 11 Bit Muxes := 40
2 Input 8 Bit Muxes := 4
2 Input 7 Bit Muxes := 2
2 Input 6 Bit Muxes := 42
2 Input 5 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 49
Module Frontend
Detailed RTL Component Info :
+---Adders :
2 Input 40 Bit Adders := 1
+---Registers :
40 Bit Registers := 2
39 Bit Registers := 1
7 Bit Registers := 1
6 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 9
+---Muxes :
2 Input 40 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module BufferedBroadcastVoluntaryReleaseTracker
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 3
2 Input 1 Bit Adders := 2
+---Registers :
64 Bit Registers := 8
26 Bit Registers := 1
8 Bit Registers := 2
4 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 8 Bit Muxes := 3
2 Input 4 Bit Muxes := 3
2 Input 1 Bit Muxes := 19
Module Queue_4
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 2
4 Bit RAMs := 2
2 Bit RAMs := 1
Module BufferedBroadcastAcquireTracker
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 9
2 Input 1 Bit Adders := 5
+---Registers :
64 Bit Registers := 8
26 Bit Registers := 1
8 Bit Registers := 12
5 Bit Registers := 1
3 Bit Registers := 11
2 Bit Registers := 3
1 Bit Registers := 9
+---Muxes :
2 Input 64 Bit Muxes := 34
2 Input 26 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 39
7 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 8
5 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 5
9 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 77
6 Input 1 Bit Muxes := 1
Module Queue_4__3
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 2
4 Bit RAMs := 2
2 Bit RAMs := 1
Module BufferedBroadcastAcquireTracker_1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 9
2 Input 1 Bit Adders := 5
+---Registers :
64 Bit Registers := 8
26 Bit Registers := 1
8 Bit Registers := 12
5 Bit Registers := 1
3 Bit Registers := 11
2 Bit Registers := 3
1 Bit Registers := 9
+---Muxes :
2 Input 64 Bit Muxes := 34
2 Input 26 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 39
7 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 8
5 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 5
9 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 77
6 Input 1 Bit Muxes := 1
Module Queue_4__2
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 2
4 Bit RAMs := 2
2 Bit RAMs := 1
Module BufferedBroadcastAcquireTracker_2
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 9
2 Input 1 Bit Adders := 5
+---Registers :
64 Bit Registers := 8
26 Bit Registers := 1
8 Bit Registers := 12
5 Bit Registers := 1
3 Bit Registers := 11
2 Bit Registers := 3
1 Bit Registers := 9
+---Muxes :
2 Input 64 Bit Muxes := 34
2 Input 26 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 39
7 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 8
5 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 5
9 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 77
6 Input 1 Bit Muxes := 1
Module Queue_4__1
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 2
4 Bit RAMs := 2
2 Bit RAMs := 1
Module BufferedBroadcastAcquireTracker_3
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 9
2 Input 1 Bit Adders := 5
+---Registers :
64 Bit Registers := 8
26 Bit Registers := 1
8 Bit Registers := 12
5 Bit Registers := 1
3 Bit Registers := 11
2 Bit Registers := 3
1 Bit Registers := 9
+---Muxes :
2 Input 64 Bit Muxes := 34
2 Input 26 Bit Muxes := 1
2 Input 11 Bit Muxes := 6
2 Input 8 Bit Muxes := 39
7 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 8
5 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 5
9 Input 2 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 77
6 Input 1 Bit Muxes := 1
Module LockingRRArbiter_5
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module LockingRRArbiter_6
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module LockingRRArbiter_7
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 2
+---Muxes :
10 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module LockingRRArbiter_8
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 6
Module L2BroadcastHub
Detailed RTL Component Info :
+---Muxes :
2 Input 5 Bit Muxes := 2
6 Input 5 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module FinishQueue_3
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 1
2 Bit RAMs := 1
Module FinishUnit
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 2
Module FinishQueue_3__1
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
6 Bit RAMs := 1
2 Bit RAMs := 1
Module FinishUnit_1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 2
Module LockingRRArbiter
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module LockingRRArbiter_1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module LockingRRArbiter_2
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 1
+---Muxes :
9 Input 3 Bit Muxes := 1
Module LockingRRArbiter_3
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
+---Muxes :
10 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 6
Module LockingRRArbiter_4
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 1
+---Muxes :
9 Input 3 Bit Muxes := 1
Module PortedTileLinkCrossbar
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 25
Module MMIOTileLinkManager
Detailed RTL Component Info :
+---Registers :
6 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 8
1 Bit Registers := 1
+---Muxes :
2 Input 6 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
5 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
4 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 6
Module LockingRRArbiter_9
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 11 Bit Muxes := 1
2 Input 3 Bit Muxes := 4
2 Input 1 Bit Muxes := 7
Module ReorderQueue__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 8
+---RAMs :
8 Bit RAMs := 1
+---Muxes :
2 Input 1 Bit Muxes := 25
Module ReorderQueue
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 8
+---RAMs :
8 Bit RAMs := 1
+---Muxes :
2 Input 1 Bit Muxes := 25
Module ClientTileLinkIOUnwrapper
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module Queue_8
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
11 Bit Registers := 1
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
Module Queue_9
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 3
Module LockingRRArbiter_10
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 9
Module ClientUncachedTileLinkIORouter
Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module LockingRRArbiter_10__1
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 9
Module ClientUncachedTileLinkIORouter_1
Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module Queue_8__1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
11 Bit Registers := 1
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
Module PLIC
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
7 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
Module DebugModule
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
2 Input 1 Bit Adders := 1
+---Registers :
64 Bit Registers := 1
34 Bit Registers := 1
11 Bit Registers := 1
10 Bit Registers := 2
6 Bit Registers := 1
3 Bit Registers := 4
2 Bit Registers := 1
1 Bit Registers := 9
+---RAMs :
512 Bit RAMs := 1
+---Muxes :
2 Input 64 Bit Muxes := 6
13 Input 64 Bit Muxes := 1
2 Input 60 Bit Muxes := 1
2 Input 56 Bit Muxes := 1
2 Input 34 Bit Muxes := 5
2 Input 32 Bit Muxes := 2
2 Input 10 Bit Muxes := 1
2 Input 8 Bit Muxes := 2
2 Input 3 Bit Muxes := 4
7 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 26
Module Queue_11
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
11 Bit Registers := 1
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
Module Queue_12
Detailed RTL Component Info :
+---Registers :
26 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 1
Module Queue_13
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
52 Bit RAMs := 1
6 Bit RAMs := 2
4 Bit RAMs := 1
2 Bit RAMs := 1
Module Queue_14
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
8 Bit RAMs := 1
6 Bit RAMs := 2
4 Bit RAMs := 1
2 Bit RAMs := 2
Module Queue_11__1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
11 Bit Registers := 1
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 2
Module Queue_16
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
8 Bit RAMs := 1
6 Bit RAMs := 2
4 Bit RAMs := 1
2 Bit RAMs := 1
Module TLXbar_peripheryBus
Detailed RTL Component Info :
+---Adders :
3 Input 4 Bit Adders := 1
+---XORs :
2 Input 26 Bit XORs := 2
+---Registers :
4 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 46 Bit Muxes := 2
2 Input 4 Bit Muxes := 4
2 Input 1 Bit Muxes := 5
Module TLLegacy_legacy
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
+---Muxes :
10 Input 26 Bit Muxes := 1
2 Input 26 Bit Muxes := 7
2 Input 8 Bit Muxes := 9
10 Input 8 Bit Muxes := 1
2 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
4 Input 3 Bit Muxes := 2
10 Input 3 Bit Muxes := 2
2 Input 3 Bit Muxes := 32
2 Input 2 Bit Muxes := 8
3 Input 2 Bit Muxes := 2
Module TLAtomicAutomata_peripheryBus
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
3 Input 3 Bit Adders := 1
+---Registers :
64 Bit Registers := 2
26 Bit Registers := 1
8 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 2
1 Bit Registers := 4
+---Muxes :
2 Input 109 Bit Muxes := 2
2 Input 64 Bit Muxes := 5
5 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 4
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 14
Module Queue
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
52 Bit RAMs := 1
16 Bit RAMs := 1
6 Bit RAMs := 3
4 Bit RAMs := 1
Module Queue_1
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
6 Bit RAMs := 3
4 Bit RAMs := 2
2 Bit RAMs := 2
Module Repeater
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
8 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module TLWidthWidget_peripheryBus
Detailed RTL Component Info :
+---Adders :
2 Input 1 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
5 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 2
2 Input 4 Bit Muxes := 2
2 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 1
Module TLHintHandler_peripheryBus
Detailed RTL Component Info :
+---Adders :
3 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 79 Bit Muxes := 2
2 Input 3 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module TLROM_bootrom
Detailed RTL Component Info :
+---Muxes :
1019 Input 32 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
6 Input 26 Bit Muxes := 1
Module Repeater_1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
13 Bit Registers := 1
4 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 32 Bit Muxes := 1
2 Input 13 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module TLFragmenter_bootrom
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 2
+---Registers :
4 Bit Registers := 2
3 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 4 Bit Muxes := 4
2 Input 3 Bit Muxes := 2
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module CoreplexLocalInterrupter_clint
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 1
+---Registers :
32 Bit Registers := 4
1 Bit Registers := 1
+---Muxes :
4 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 3
2 Input 1 Bit Muxes := 1
Module Repeater_2
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 3
Module TLWidthWidget_clint
Detailed RTL Component Info :
+---Adders :
2 Input 1 Bit Adders := 1
+---Registers :
32 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
5 Input 64 Bit Muxes := 1
2 Input 32 Bit Muxes := 2
2 Input 8 Bit Muxes := 1
5 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 1
Module Repeater__1
Detailed RTL Component Info :
+---Registers :
64 Bit Registers := 1
26 Bit Registers := 1
8 Bit Registers := 1
3 Bit Registers := 3
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 26 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 3
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module TLFragmenter_clint
Detailed RTL Component Info :
+---Adders :
3 Input 3 Bit Adders := 1
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 3
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 1
2 Input 3 Bit Muxes := 5
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
Module LockingRRArbiter_12
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 2
Module ClientUncachedTileLinkIORouter_2
Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 1
Module ReorderQueue_2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 8
+---RAMs :
24 Bit RAMs := 1
8 Bit RAMs := 1
+---Muxes :
2 Input 1 Bit Muxes := 27
Module LockingArbiter_2
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
+---Registers :
3 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 64 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 3 Bit Muxes := 2
2 Input 1 Bit Muxes := 10
Module NastiIOTileLinkIOConverter
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 3
+---Registers :
5 Bit Registers := 1
3 Bit Registers := 3
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 2
2 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 6
Module Queue_17__1
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 3
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 3
Module Queue_17
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
8 Bit Registers := 1
5 Bit Registers := 1
4 Bit Registers := 3
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 3
Module Queue_19
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
16 Bit RAMs := 1
10 Bit RAMs := 1
2 Bit RAMs := 2
Module Queue_20
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
128 Bit RAMs := 1
10 Bit RAMs := 1
4 Bit RAMs := 1
2 Bit RAMs := 2
Module Queue_21
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
Module SerialAdapter
Detailed RTL Component Info :
+---Adders :
2 Input 64 Bit Adders := 2
3 Input 64 Bit Adders := 1
2 Input 29 Bit Adders := 1
14 Input 8 Bit Adders := 1
16 Input 5 Bit Adders := 2
8 Input 4 Bit Adders := 2
4 Input 3 Bit Adders := 2
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 1
+---Registers :
64 Bit Registers := 2
32 Bit Registers := 3
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 95 Bit Muxes := 3
2 Input 66 Bit Muxes := 1
3 Input 64 Bit Muxes := 1
2 Input 64 Bit Muxes := 18
2 Input 32 Bit Muxes := 5
2 Input 11 Bit Muxes := 1
6 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 40
2 Input 3 Bit Muxes := 28
2 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 13
5 Input 1 Bit Muxes := 1
Module Queue_22__1
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
64 Bit RAMs := 1
Module Queue_22
Detailed RTL Component Info :
+---Adders :
3 Input 1 Bit Adders := 1
2 Input 1 Bit Adders := 2
+---Registers :
1 Bit Registers := 1
+---RAMs :
64 Bit RAMs := 1
Module FPGAZynqTop
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
+---Muxes :
2 Input 1 Bit Muxes := 1
Module Queue_24
Detailed RTL Component Info :
+---Registers :
32 Bit Registers := 1
12 Bit Registers := 1
8 Bit Registers := 1
4 Bit Registers := 3
3 Bit Registers := 2
2 Bit Registers := 1
1 Bit Registers := 3
Module Queue_25
Detailed RTL Component Info :
+---Registers :
12 Bit Registers := 1
1 Bit Registers := 1
Module NastiErrorSlave
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
2 Input 8 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
Module RRArbiter_1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
+---Muxes :
3 Input 12 Bit Muxes := 1
5 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 2
Module HellaPeekingArbiter
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
3 Input 32 Bit Muxes := 1
3 Input 12 Bit Muxes := 1
2 Input 2 Bit Muxes := 6
3 Input 2 Bit Muxes := 1
3 Input 1 Bit Muxes := 3
2 Input 1 Bit Muxes := 2
Module NastiRouter
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
+---Muxes :
2 Input 1 Bit Muxes := 2
Module Queue_26__1
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 3
3 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 1
+---RAMs :
512 Bit RAMs := 1
Module Queue_26
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 3
3 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 2
1 Bit Registers := 1
+---RAMs :
512 Bit RAMs := 1
Module NastiFIFO
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
2 Input 5 Bit Adders := 1
+---Registers :
12 Bit Registers := 2
8 Bit Registers := 1
2 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
4 Input 32 Bit Muxes := 1
2 Input 8 Bit Muxes := 1
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
Module ResetController
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
12 Bit Registers := 2
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 2
+---Muxes :
4 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 5
Module axi_protocol_converter_v2_1_9_b_downsizer
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
4 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 4
Module reset_blk_ramfifo
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 2
1 Bit Registers := 10
Module dmem
Detailed RTL Component Info :
+---Registers :
10 Bit Registers := 1
Module memory
Detailed RTL Component Info :
+---Registers :
10 Bit Registers := 1
Module rd_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__3
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module rd_status_flags_ss
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module rd_fwft
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__1
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare__2
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module wr_status_flags_ss
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module reset_blk_ramfifo__2
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 2
1 Bit Registers := 10
Module dmem__parameterized0
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module memory__parameterized0
Detailed RTL Component Info :
+---Registers :
5 Bit Registers := 1
Module rd_bin_cntr__2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__11
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare__10
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module rd_status_flags_ss__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module rd_fwft__2
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr__2
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__7
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare__6
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module wr_status_flags_ss__2
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi_protocol_converter_v2_1_9_a_axi3_conv
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
2 Input 6 Bit Adders := 2
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 3
16 Bit Registers := 1
12 Bit Registers := 1
8 Bit Registers := 1
6 Bit Registers := 4
4 Bit Registers := 4
3 Bit Registers := 2
2 Bit Registers := 3
1 Bit Registers := 11
+---Muxes :
8 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
8 Input 12 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 10
Module axi_protocol_converter_v2_1_9_w_axi3_conv
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 1
+---Registers :
8 Bit Registers := 1
1 Bit Registers := 1
+---Muxes :
2 Input 8 Bit Muxes := 2
Module reset_blk_ramfifo__1
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 2
1 Bit Registers := 10
Module dmem__parameterized1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module memory__parameterized1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module rd_bin_cntr__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__9
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare__8
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module rd_status_flags_ss__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module rd_fwft__1
Detailed RTL Component Info :
+---Registers :
2 Bit Registers := 1
1 Bit Registers := 5
+---Muxes :
2 Input 2 Bit Muxes := 4
5 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
3 Input 1 Bit Muxes := 1
4 Input 1 Bit Muxes := 2
Module wr_bin_cntr__1
Detailed RTL Component Info :
+---Adders :
2 Input 5 Bit Adders := 1
+---Registers :
5 Bit Registers := 2
Module compare__5
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module compare__4
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 5
Module wr_status_flags_ss__1
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 2
Module axi_protocol_converter_v2_1_9_a_axi3_conv__parameterized0
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 3
16 Bit Registers := 1
12 Bit Registers := 1
8 Bit Registers := 1
6 Bit Registers := 3
4 Bit Registers := 4
3 Bit Registers := 2
2 Bit Registers := 3
1 Bit Registers := 10
+---Muxes :
8 Input 32 Bit Muxes := 1
2 Input 32 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
8 Input 12 Bit Muxes := 1
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
3 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 8
Module lpf
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 3
Module upcnt_n
Detailed RTL Component Info :
+---Adders :
2 Input 6 Bit Adders := 1
+---Registers :
6 Bit Registers := 1
+---Muxes :
2 Input 6 Bit Muxes := 1
2 Input 1 Bit Muxes := 1
Module sequence_psr
Detailed RTL Component Info :
+---Registers :
3 Bit Registers := 3
1 Bit Registers := 5
Module proc_sys_reset
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 5
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Start Parallel Synthesis Optimization : Time (s): cpu = 00:01:48 ; elapsed = 00:02:42 . Memory (MB): peak = 1864.160 ; gain = 981.125 ; free physical = 71 ; free virtual = 2648
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
DSP Report: Generating DSP fma/_T_16, operation Mode is: A*B2.
DSP Report: register B is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
WARNING: [Synth 8-3936] Found unconnected internal register '_T_161_cmd_reg' and it is trimmed from '5' to '3' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:115131]
WARNING: [Synth 8-3936] Found unconnected internal register '_T_163_cmd_reg' and it is trimmed from '5' to '4' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:116583]
DSP Report: Generating DSP fma/_T_16, operation Mode is: A*B2.
DSP Report: register B is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: PCIN+A*B.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: (PCIN>>17)+A*B2.
DSP Report: register B is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: A*B2.
DSP Report: register B is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: PCIN+A2*B.
DSP Report: register A is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: PCIN+A*B.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: A2*B.
DSP Report: register A is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: (PCIN>>17)+A2*B.
DSP Report: register A is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP fma/_T_16, operation Mode is: PCIN+A2*B.
DSP Report: register A is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: operator fma/_T_16 is absorbed into DSP fma/_T_16.
DSP Report: Generating DSP mul/_T_23, operation Mode is: A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: PCIN+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: (PCIN>>17)+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: PCIN+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: PCIN+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: (PCIN>>17)+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: Generating DSP mul/_T_23, operation Mode is: PCIN+A''*B''.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register B is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: register A is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
DSP Report: operator mul/_T_23 is absorbed into DSP mul/_T_23.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP _T_159, operation Mode is: A2*B2.
DSP Report: register B is absorbed into DSP _T_159.
DSP Report: register A is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: Generating DSP _T_159, operation Mode is: (PCIN>>17)+A2*B2.
DSP Report: register B is absorbed into DSP _T_159.
DSP Report: register A is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: Generating DSP _T_159, operation Mode is: A2*B2.
DSP Report: register B is absorbed into DSP _T_159.
DSP Report: register A is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: Generating DSP _T_159, operation Mode is: (PCIN>>17)+A2*B2.
DSP Report: register B is absorbed into DSP _T_159.
DSP Report: register A is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
DSP Report: operator _T_159 is absorbed into DSP _T_159.
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:102299]
WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:103179]
WARNING: [Synth 8-3936] Found unconnected internal register '_T_1036_br_pc_reg' and it is trimmed from '39' to '2' bits. [/home/alpha/fpga-zynq/zedboard/src/verilog/Top.ZynqConfig.v:95780]
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3917] design L2BroadcastHub has port io_outer_probe_ready driven by constant 0
WARNING: [Synth 8-3917] design L2BroadcastHub has port io_outer_finish_valid driven by constant 0
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:01:58 ; elapsed = 00:03:09 . Memory (MB): peak = 1866.172 ; gain = 983.137 ; free physical = 86 ; free virtual = 2507
---------------------------------------------------------------------------------
Finished Parallel Reinference : Time (s): cpu = 00:01:58 ; elapsed = 00:03:09 . Memory (MB): peak = 1866.172 ; gain = 983.137 ; free physical = 86 ; free virtual = 2507
Report RTL Partitions:
+------+------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+------------------------+------------+----------+
|1 |FPU__GB0 | 1| 40751|
|2 |FPU__GB1 | 1| 39062|
|3 |RocketTile__GCB0 | 1| 34841|
|4 |HellaCache | 1| 17169|
|5 |RocketTile__GCB2 | 1| 15783|
|6 |L2BroadcastHub | 1| 50716|
|7 |DefaultCoreplex__GCB1 | 1| 6977|
|8 |FPGAZynqTop__GC0 | 1| 15360|
|9 |ZynqAXISlave | 1| 841|
|10 |rocketchip_wrapper__GC0 | 1| 2498|
+------+------------------------+------------+----------+
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Block RAM: Preliminary Mapping Report (see note below)
+--------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+--------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|MSHRFile | sdq_reg | 32 x 64(READ_FIRST) | W | | 32 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|MetadataArray | _T_2352_0_reg | 64 x 22(READ_FIRST) | W | | 64 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MetadataArray | _T_2352_1_reg | 64 x 22(READ_FIRST) | W | | 64 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MetadataArray | _T_2352_2_reg | 64 x 22(READ_FIRST) | W | | 64 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|MetadataArray | _T_2352_3_reg | 64 x 22(READ_FIRST) | W | | 64 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|DataArray | _T_744_0_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|DataArray | _T_811_0_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|DataArray | _T_878_0_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|DataArray | _T_945_0_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|ICache | tag_array_1_reg | 64 x 20(READ_FIRST) | W | | 64 x 20(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|ICache | tag_array_2_reg | 64 x 20(READ_FIRST) | W | | 64 x 20(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|ICache | tag_array_3_reg | 64 x 20(READ_FIRST) | W | | 64 x 20(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|ICache | tag_array_0_reg | 64 x 20(READ_FIRST) | W | | 64 x 20(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|ICache | _T_1178_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|ICache | _T_1197_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|ICache | _T_1216_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
|ICache | _T_1159_reg | 512 x 64(READ_FIRST) | W | | 512 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
+--------------+-----------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------------------------+----------------------------------------------------------------------------------+----------------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------------------------+----------------------------------------------------------------------------------+----------------+----------------------+-----------------+
|MSHRFile | MSHR/rpq/ram_addr_reg | Implied | 16 x 6 | RAM32M x 1 |
|MSHRFile | MSHR/rpq/ram_tag_reg | Implied | 16 x 7 | RAM32M x 2 |
|MSHRFile | MSHR/rpq/ram_cmd_reg | Implied | 16 x 5 | RAM32M x 1 |
|MSHRFile | MSHR/rpq/ram_typ_reg | Implied | 16 x 3 | RAM32M x 1 |
|MSHRFile | MSHR/rpq/ram_sdq_id_reg | Implied | 16 x 5 | RAM32M x 1 |
|MSHRFile | MSHR_1/rpq/ram_addr_reg | Implied | 16 x 6 | RAM32M x 1 |
|MSHRFile | MSHR_1/rpq/ram_tag_reg | Implied | 16 x 7 | RAM32M x 2 |
|MSHRFile | MSHR_1/rpq/ram_cmd_reg | Implied | 16 x 5 | RAM32M x 1 |
|MSHRFile | MSHR_1/rpq/ram_typ_reg | Implied | 16 x 3 | RAM32M x 1 |
|MSHRFile | MSHR_1/rpq/ram_sdq_id_reg | Implied | 16 x 5 | RAM32M x 1 |
|Rocket | _T_6759_reg | Implied | 32 x 64 | RAM32M x 22 |
|BTB | _T_2795_reg | Implied | 128 x 2 | RAM128X1D x 2 |
|BufferedBroadcastAcquireTracker | ignt_q/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker | ignt_q/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker | ignt_q/ram_client_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker | ignt_q/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|BufferedBroadcastAcquireTracker | ignt_q/ram_a_type_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_1 | ignt_q/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_1 | ignt_q/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_1 | ignt_q/ram_client_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_1 | ignt_q/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|BufferedBroadcastAcquireTracker_1 | ignt_q/ram_a_type_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_2 | ignt_q/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_2 | ignt_q/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_2 | ignt_q/ram_client_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_2 | ignt_q/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|BufferedBroadcastAcquireTracker_2 | ignt_q/ram_a_type_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_3 | ignt_q/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_3 | ignt_q/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|BufferedBroadcastAcquireTracker_3 | ignt_q/ram_client_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|BufferedBroadcastAcquireTracker_3 | ignt_q/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|BufferedBroadcastAcquireTracker_3 | ignt_q/ram_a_type_reg | Implied | 2 x 3 | RAM32M x 1 |
|PortedTileLinkCrossbar | ClientUncachedTileLinkNetworkPort/finisher/FinishQueue/ram_manager_xact_id_reg | Implied | 2 x 3 | RAM32M x 1 |
|PortedTileLinkCrossbar | ClientUncachedTileLinkNetworkPort/finisher/FinishQueue/ram_manager_id_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|PortedTileLinkCrossbar | ClientUncachedTileLinkNetworkPort_1/finisher/FinishQueue/ram_manager_xact_id_reg | Implied | 2 x 3 | RAM32M x 1 |
|PortedTileLinkCrossbar | ClientUncachedTileLinkNetworkPort_1/finisher/FinishQueue/ram_manager_id_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|ClientTileLinkIOUnwrapper | acqRoq/_T_40_reg | Implied | 8 x 1 | RAM16X1D x 1 |
|DebugModule | ramMem_reg | Implied | 8 x 64 | RAM16X1S x 64 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_addr_block_reg | Implied | 2 x 26 | RAM32M x 5 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_voluntary_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_r_type_reg | Implied | 2 x 3 | RAM32M x 1 |
|ClientTileLinkEnqueuer_1 | Queue_2/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_manager_xact_id_reg | Implied | 2 x 3 | RAM32M x 1 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_g_type_reg | Implied | 2 x 4 | RAM32M x 1 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|ClientTileLinkEnqueuer_1 | Queue_3/ram_manager_id_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_addr_beat_reg | Implied | 2 x 3 | RAM32M x 1 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_client_xact_id_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_manager_xact_id_reg | Implied | 2 x 3 | RAM32M x 1 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_is_builtin_type_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_g_type_reg | Implied | 2 x 4 | RAM32M x 1 |
|rocketchip_wrapper | ClientUncachedTileLinkEnqueuer_1/Queue_1/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|TLBuffer_peripheryBus | Queue/ram_opcode_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue/ram_param_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue/ram_size_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue/ram_source_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|TLBuffer_peripheryBus | Queue/ram_address_reg | Implied | 2 x 26 | RAM32M x 5 |
|TLBuffer_peripheryBus | Queue/ram_mask_reg | Implied | 2 x 8 | RAM32M x 2 |
|TLBuffer_peripheryBus | Queue/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|TLBuffer_peripheryBus | Queue_1/ram_opcode_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue_1/ram_param_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|TLBuffer_peripheryBus | Queue_1/ram_size_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue_1/ram_source_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|TLBuffer_peripheryBus | Queue_1/ram_sink_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|TLBuffer_peripheryBus | Queue_1/ram_addr_lo_reg | Implied | 2 x 3 | RAM32M x 1 |
|TLBuffer_peripheryBus | Queue_1/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|TLBuffer_peripheryBus | Queue_1/ram_error_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|NastiIOTileLinkIOConverter | roq/_T_238_addr_beat_reg | Implied | 8 x 3 | RAM32M x 1 |
|NastiIOTileLinkIOConverter | roq/_T_238_subblock_reg | Implied | 8 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | Queue_2/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|rocketchip_wrapper | Queue_2/ram_last_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | Queue_2/ram_id_reg | Implied | 2 x 5 | RAM32M x 1 |
|rocketchip_wrapper | Queue_2/ram_strb_reg | Implied | 2 x 8 | RAM32M x 2 |
|rocketchip_wrapper | Queue_2/ram_user_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | Queue_3/ram_resp_reg | Implied | 2 x 2 | RAM16X1D x 2 |
|rocketchip_wrapper | Queue_3/ram_data_reg | Implied | 2 x 64 | RAM32M x 11 |
|rocketchip_wrapper | Queue_3/ram_last_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | Queue_3/ram_id_reg | Implied | 2 x 5 | RAM32M x 1 |
|rocketchip_wrapper | Queue_3/ram_user_reg | Implied | 2 x 1 | RAM16X1D x 1 |
|rocketchip_wrapper | Queue_5/ram_reg | Implied | 2 x 32 | RAM32M x 6 |
|rocketchip_wrapper | Queue_6/ram_reg | Implied | 2 x 32 | RAM32M x 6 |
|ZynqAXISlave | fifo/outq/ram_reg | Implied | 16 x 32 | RAM32M x 6 |
|ZynqAXISlave | fifo/inq/ram_reg | Implied | 16 x 32 | RAM32M x 6 |
|fifo_generator_v13_1_1 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 10 | RAM32M x 2 |
|fifo_generator_v13_1_1 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 5 | RAM32M x 1 |
|fifo_generator_v13_1_1 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 1 | RAM32X1D x 1 |
+----------------------------------+----------------------------------------------------------------------------------+----------------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below)
+--------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+--------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|FPUFMAPipe | A*B2 | 25 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|MulAddRecFN | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | A*B2 | 20 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | (PCIN>>17)+A*B2 | 20 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | A*B2 | 20 | 18 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | PCIN+A2*B | 18 | 18 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | A2*B | 18 | 18 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | (PCIN>>17)+A2*B | 18 | 18 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|FPUFMAPipe_1 | PCIN+A2*B | 18 | 18 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | A''*B'' | 21 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | PCIN+A''*B'' | 21 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | (PCIN>>17)+A''*B'' | 21 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | A''*B'' | 21 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | PCIN+A''*B'' | 18 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | PCIN+A''*B'' | 21 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | A''*B'' | 18 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | (PCIN>>17)+A''*B'' | 18 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|DivSqrtRecF64 | PCIN+A''*B'' | 18 | 18 | - | - | 48 | 2 | 2 | - | - | - | 0 | 0 |
|MulDiv | A2*B2 | 18 | 9 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MulDiv | (PCIN>>17)+A2*B2 | 14 | 9 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MulDiv | A2*B2 | 18 | 9 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 9 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
+--------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_access_reg[0]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[0]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (DefaultCoreplexi_4/DebugModule/\CONTROLReg_access_reg[1] )
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_access_reg[2]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_autoincrement_reg' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[0]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[1]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[1]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[2]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_buserror_reg[2]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[0]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[1]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[2]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[3]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[4]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[5]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[6]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[7]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[8]' (FDRE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_reserved0_reg[9]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (DefaultCoreplexi_4/DebugModule/\CONTROLReg_reserved0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (DefaultCoreplexi_4/PLIC/\_T_589_reg[0] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (DefaultCoreplexi_4/PLIC/\_T_589_reg[1] )
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/PortedTileLinkCrossbar/prbNet/arb/lastGrant_reg[0]' (FDE) to 'DefaultCoreplexi_4/PortedTileLinkCrossbar/prbNet/arb/lastGrant_reg[1]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (DefaultCoreplexi_4/PortedTileLinkCrossbar/\prbNet/arb/lastGrant_reg[1] )
WARNING: [Synth 8-3332] Sequential element (relNet/arb/lastGrant_reg[0]) is unused and will be removed from module PortedTileLinkCrossbar.
WARNING: [Synth 8-3332] Sequential element (prbNet/arb/lastGrant_reg[2]) is unused and will be removed from module PortedTileLinkCrossbar.
WARNING: [Synth 8-3332] Sequential element (prbNet/arb/lastGrant_reg[1]) is unused and will be removed from module PortedTileLinkCrossbar.
WARNING: [Synth 8-3332] Sequential element (prbNet/arb/lastGrant_reg[0]) is unused and will be removed from module PortedTileLinkCrossbar.
WARNING: [Synth 8-3332] Sequential element (xact_pending_reg[5]) is unused and will be removed from module MMIOTileLinkManager.
WARNING: [Synth 8-3332] Sequential element (xact_pending_reg[4]) is unused and will be removed from module MMIOTileLinkManager.
WARNING: [Synth 8-3332] Sequential element (_T_589_reg[1]) is unused and will be removed from module PLIC.
WARNING: [Synth 8-3332] Sequential element (_T_589_reg[0]) is unused and will be removed from module PLIC.
WARNING: [Synth 8-3332] Sequential element (sbAcqReg_union_reg[10]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (sbAcqReg_union_reg[9]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (sbAcqReg_union_reg[0]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_access_reg[1]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_autoincrement_reg) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_buserror_reg[0]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_access_reg[0]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_access_reg[2]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_buserror_reg[1]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_buserror_reg[2]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[9]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[0]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[1]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[2]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[3]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[4]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[5]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[6]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[7]) is unused and will be removed from module DebugModule.
WARNING: [Synth 8-3332] Sequential element (CONTROLReg_reserved0_reg[8]) is unused and will be removed from module DebugModule.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_len_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/ram_id_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/r_queue/maybe_full_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/ram_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/b_queue/maybe_full_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\top/slave /\xbar/NastiRouter/err_slave/draining_reg )
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/maybe_full_reg) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/maybe_full_reg) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/draining_reg) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[7]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[6]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[5]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[4]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[3]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[2]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[1]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_len_reg[0]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[7]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[6]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[5]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[4]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[3]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[2]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[1]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/beats_left_reg[0]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/responding_reg) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[11]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[10]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[9]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[8]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[7]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[6]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[5]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[4]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[3]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[2]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[1]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/b_queue/ram_reg[0]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[11]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[10]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[9]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[8]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[7]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[6]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[5]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[4]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[3]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[2]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[1]) is unused and will be removed from module ZynqAXISlave.
WARNING: [Synth 8-3332] Sequential element (xbar/NastiRouter/err_slave/r_queue/ram_id_reg[0]) is unused and will be removed from module ZynqAXISlave.
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/addr_step_q_reg[0]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/addr_step_q_reg[1]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/addr_step_q_reg[2]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/addr_step_q_reg[3]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[12]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[13]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[13]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[14]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/first_step_q_reg[15] )
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/addr_step_q_reg[0]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/addr_step_q_reg[1]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/addr_step_q_reg[2]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/addr_step_q_reg[3]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[12]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[13]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[13]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[14]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[15] )
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALEN_Q_reg[7]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/num_transactions_q_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALEN_Q_reg[4]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/num_transactions_q_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALEN_Q_reg[5]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/num_transactions_q_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALEN_Q_reg[6]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/num_transactions_q_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/areset_d_reg[0]' (FD) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/areset_d_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/areset_d_reg[1]' (FD) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/areset_d_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[7]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/num_transactions_q_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[4]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/num_transactions_q_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[5]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/num_transactions_q_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[6]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/num_transactions_q_reg[2]'
INFO: [Synth 8-3333] propagating constant 1 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/NO_B_CHANNEL.cmd_b_empty_reg )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALOCK_Q_reg[1] )
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[7]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[8]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[8]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[9]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[9]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[10]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[10]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[11]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[11]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[12]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[12]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[13]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[13]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[14]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[14]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[15]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[15]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[16]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[16]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[17]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[17]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[18]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[18]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[19]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[19]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[20]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[20]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[21]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[21]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[22]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[22]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[23]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[23]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[24]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[24]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[25]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[25]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[26]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[26]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[27]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[27]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[28]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[28]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[29]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[29]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[30]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[30]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_6/system_i/axi_interconnect_1/\s00_couplers/auto_pc /\inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALOCK_Q_reg[1] )
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[7]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[8]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[9]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[10]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[11]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[12]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[13]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[14]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[15]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[16]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[17]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[18]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[19]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[20]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[21]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[22]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[23]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[24]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[25]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[26]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[27]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[28]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[29]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[30]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[31]'
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[30]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[29]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[28]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[27]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[26]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[25]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[24]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[23]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[22]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[21]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[20]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[19]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[18]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[17]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[16]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[15]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[14]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[13]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[12]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[11]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[10]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[9]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[8]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[7]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/first_step_q_reg[15]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALOCK_Q_reg[1]) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/NO_B_CHANNEL.cmd_b_empty_reg) is unused and will be removed from module system_auto_pc_1.
INFO: [Synth 8-3332] Sequential element (inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[30]) is unused and will be removed from module system_auto_pc_1.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3886] merging instance 'i_6/system_i/proc_sys_reset_0/U0/SEQ/pr_dec_reg[1]' (FD) to 'i_6/system_i/proc_sys_reset_0/U0/SEQ/bsr_dec_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/proc_sys_reset_0/U0/SEQ/bsr_dec_reg[1]' (FD) to 'i_6/system_i/proc_sys_reset_0/U0/SEQ/core_dec_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/addr_step_q_reg[4]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/addr_step_q_reg[4]' (FDRE) to 'i_6/system_i/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/size_mask_q_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[9]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[8]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[7]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[5]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[6]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[0]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[1]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[1]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[2]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[2]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[3]'
INFO: [Synth 8-3886] merging instance 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[3]' (FDE) to 'DefaultCoreplexi_4/DebugModule/CONTROLReg_hartid_reg[4]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (DefaultCoreplexi_4/DebugModule/\CONTROLReg_hartid_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (FPUFMAPipe/\_T_205_exc_reg[3] )
INFO: [Synth 8-3886] merging instance 'sfma/_T_205_data_reg[33]' (FDE) to 'sfma/_T_205_data_reg[34]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 1 across sequential element (sfma/\_T_205_data_reg[64] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (sfma/\_T_205_exc_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\_T_386_exc_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\_T_735_exc_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (FPUFMAPipe/\_T_214_exc_reg[3] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (sfma/\_T_214_data_reg[64] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (sfma/\_T_214_exc_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (FPUFMAPipe/\_T_223_exc_reg[3] )
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[62] )
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_2_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_3_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_1_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_7_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_6_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_4_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\PTW/_T_2431_5_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[32] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[33] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[34] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[35] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[36] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[37] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[38] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_reserved_reg[39] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[2] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_maskmax_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_maskmax_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_ttype_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_ttype_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_ttype_reg[1] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_bp_0_control_ttype_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_ttype_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_ttype_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_1_control_ttype_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_bp_0_control_ttype_reg[3] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:02:37 ; elapsed = 00:09:10 . Memory (MB): peak = 2396.250 ; gain = 1513.215 ; free physical = 84 ; free virtual = 591
---------------------------------------------------------------------------------
Finished Parallel Area Optimization : Time (s): cpu = 00:02:37 ; elapsed = 00:09:10 . Memory (MB): peak = 2396.250 ; gain = 1513.215 ; free physical = 83 ; free virtual = 591
Report RTL Partitions:
+------+------------------------+------------+----------+
| |RTL Partition |Replication |Instances |
+------+------------------------+------------+----------+
|1 |FPU__GB0 | 1| 27150|
|2 |FPU__GB1 | 1| 22422|
|3 |RocketTile__GCB0 | 1| 17734|
|4 |HellaCache | 1| 9703|
|5 |RocketTile__GCB2 | 1| 11300|
|6 |L2BroadcastHub | 1| 29520|
|7 |DefaultCoreplex__GCB1 | 1| 3335|
|8 |FPGAZynqTop__GC0 | 1| 8331|
|9 |ZynqAXISlave | 1| 491|
|10 |rocketchip_wrapper__GC0 | 1| 1741|
+------+------------------------+------------+----------+
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:51 ; elapsed = 00:10:51 . Memory (MB): peak = 2724.598 ; gain = 1841.562 ; free physical = 80 ; free virtual = 264
---------------------------------------------------------------------------------
Parent process (pid /home/alpha/Xilinx/Vivado/2016.2/bin/loader: line 164: 14499 Killed "$RDI_PROG" "$@"
14499) has died. This helper process will now exit
[Wed Jul 12 06:57:40 2017] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.94 ; elapsed = 00:17:21 . Memory (MB): peak = 1269.254 ; gain = 7.906 ; free physical = 1406 ; free virtual = 2157
# launch_runs impl_1 -to_step write_bitstream
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.
INFO: [Common 17-206] Exiting Vivado at Wed Jul 12 07:00:14
from fpga-zynq.
davidbiancolin
commented on May 18, 2024
Consult this vivado forum entry.
from fpga-zynq.
ninode
commented on May 18, 2024
Thank you, I'll take a look and close the issue.
from fpga-zynq.
Related Issues (20)
- Problems with fesvr-zynq on zc702 HOT 5
- A problem when building u-boot-xlnx HOT 1
- How to extend the address size of ExtMem HOT 1
- Password not working HOT 1
- ERROR: No cores found HOT 2
- terminate called after throwing an instance of 'std::runtime_error'
- To port free rtos on rocketcore
- uEnv.txt not found
- **[error] (compile:run) Nonzero exit code: 1
- How to use update_version script
- Project Loading Failed HOT 1
- make rocket过程中遇到的问题 HOT 1
- 在rocket chip上使用buildroot配置linux时，需要账号密码 HOT 2
- Can rocket core use PS7 side FCLK0 instead of external clock input?
- How to create RAM disk image
- Compiling testchipip
- Failed to launch run 'impl_1' due to failures in the following run(s)
- PYNQ ZU support
- Newer versions of Vivado
- Newer linux kernels on bbl.
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from fpga-zynq.