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Tulio Pereira Bitencourt's Projects

arithmetic-encoder-av1 icon arithmetic-encoder-av1

This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.

neander_verilog icon neander_verilog

Hypothetical processor called Neander described using Verilog just for practice.

pampy icon pampy

Development of a processor, in Verilog, able to executes Python algorithm.

pyconv icon pyconv

Converter algorithm created to generate the memory inicialization files (.mif and .mem) for Quartus II and Modelsim based on Python Assembler code entry.

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