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12306

12306智能刷票，订票

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

captura

Capture Screen, Audio, Cursor, Mouse Clicks and Keystrokes

cluelib

A generic class library in SystemVerilog

compose-spec

The Compose specification

cppcoreguidelines

The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++

darkriscv

opensouce RISC-V implemented from scratch in one night!

emacs.d

Fast and robust Emacs setup.

emacs.d-1

An Emacs configuration bundle with batteries included

eng-practices

Google's Engineering Practices documentation

exfat

Free exFAT file system implementation

ffmpeg-builds

fizzim2

FSM (Finite State Machine) tools for Verilog HDL.

friends

Friends Transcripts

git-repo

repo - The Multiple Git Repository Tool - (mirror of https://gerrit.googlesource.com/git-repo)

gitea

Git with a cup of tea, painless self-hosted git service

gitolite

Hosting git repositories -- Gitolite allows you to setup git hosting on a central server, with very fine-grained access control and many (many!) more powerful features.

gnuradio

GNU Radio – the Free and Open Software Radio Ecosystem

greps

GNU Radio Enhancement Proposals

hdl

HDL libraries and projects

hdmi-pi

我设计的一个HDMI转MIPI模块，可以用于驱动各种手机屏幕当显示器用。

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

linux-xlnx

The official Linux kernel from Xilinx

macvim

Vim - the text editor - for macOS

mastering-emacs-in-one-year-guide

Be great at emacs in one year

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

perl5

🐫 The Perl programming language

powerline

Powerline is a statusline plugin for vim, and provides statuslines and prompts for several other applications, including zsh, bash, tmux, IPython, Awesome and Qtile.

pymacs

Emacs to Python interface

riscv-v-spec

Working draft of the proposed RISC-V V vector extension