Comments (4)
@cibomahto i'm about to break out the pynvcm.py with friends to a separate repository to separate it a bit from the rest in this repo.
Just to cross-check, it is still fine to do the write, verify and secure in one go? It seems to work fine during my tests, but got a bit curious since you mention it as three seperate steps here
./pynvcm.py --write ../application_fpga/application_fpga.bin --verify ../application_fpga/application_fpga.bin --secure --my-design-is-good-enough
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I think it's fine, the Lattice tools don't power cycle the chip between these steps.
Just note that pynvcm doesn't honor the order of operations passed to it; it has a fixed order that it evaluates them (which works for this case):
tillitis-key1/hw/production_test/pynvcm.py
Line 725 in 7cd085a
I think I wrote it as separate steps for clarity.
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Thanks, appreciate the clarity!
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pynvcm.py now lives in its own repo: https://github.com/tillitis/pynvcm
We have not removed these files from this repo, but it will most likely be done in the near future, so closing this.
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Related Issues (20)
- Clean up lint warnings. Again HOT 2
- Add context when sending device app HOT 1
- Run SPDX check in CI
- Update linter to Verilog-2005 HOT 2
- Add build of FPGA design with Icarus
- Add Icarus Verilog to tools installed HOT 2
- Try to remove all VERSION fields from cores
- Add more (security) code checkers to CI HOT 1
- Optimize FPGA design for clock frequency
- Change name of the FPGA design
- Remove outdated docs
- Verilog linter warnings
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 2
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 14
- support for OpenPGP? HOT 1
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