Comments (4)
I've created the https://github.com/tillitis/tillitis-key1/tree/cpu_configuration branch for work, and made a first stab at the clean up. However I should compare our configuration with the defaults in the CPU source code, not the documentation.
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The results from first attempt was not good. The core expanded. Deleted the branch mentioned above and create a new one. https://github.com/tillitis/tillitis-key1/tree/cpu_config_cleanup
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The new branch contains a commit that removes options in the instance that are the same as what the core has as defaults. This should be 100% benign. Interestingly, disabling ENABLE_COUNTERS64 make the core grow with one LC. We therefore keep that option enabled (is enabled as desfault). (Enabling counters makes the core grow with many LCs.)
The commit:
317561a
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The commit has been merged into main.
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Related Issues (20)
- Clean up lint warnings. Again HOT 2
- Add context when sending device app HOT 1
- Run SPDX check in CI
- Update linter to Verilog-2005 HOT 2
- Add build of FPGA design with Icarus
- Add Icarus Verilog to tools installed HOT 2
- Try to remove all VERSION fields from cores
- Add more (security) code checkers to CI HOT 1
- Optimize FPGA design for clock frequency
- Change name of the FPGA design
- Remove outdated docs
- Verilog linter warnings
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 2
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 14
- support for OpenPGP? HOT 1
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