Comments (6)
It seems like this commit was added specifically to cause that error when nothing was replaced. I'm not sure if this is the intended behavior from the TKey build code.
YosysHQ/icestorm@a4d32c9
from tillitis-key1.
Actually, this might be a general build issue on macOS. I tried building the .bin file on a clean linux install and it did replace some portions of memory.
from tillitis-key1.
Oh, that's a good change. When icebram fails to replace anything, that is most likely a fatal error. It is also for us.
But can you verify that you're building yosys itself from 06ef3f264afaa3eaeab45cc0404d8006c15f02b1 according to https://github.com/tillitis/tillitis-key1/blob/main/doc/toolchain_setup.md on both Macos and a Linux? We're sitting on that commit to avoid precisely some issue which causes icebram to fail to replace anything.
from tillitis-key1.
Sorry! It seems like brew overrode the path for yosys. I deleted the brew one, and it works now.
from tillitis-key1.
@0xMihir oh, so you had a yosys installed from brew, which took precedence over the one installed in /usr/local/bin as part of Tillitis toolchain? I guess brew as their own entry in PATH, before /usr/local/bin then? But I don't know or have access to any Macos system. Did you just uninstall yosys from brew? What is the best way to avoid the conflict? Perhaps we should document something...
from tillitis-key1.
Yes, I ran brew uninstall yosys
and reran sudo make install
after
from tillitis-key1.
Related Issues (20)
- Clean up lint warnings. Again HOT 2
- Add context when sending device app HOT 1
- Run SPDX check in CI
- Update linter to Verilog-2005 HOT 2
- Add build of FPGA design with Icarus
- Add Icarus Verilog to tools installed HOT 2
- Try to remove all VERSION fields from cores
- Add more (security) code checkers to CI HOT 1
- Optimize FPGA design for clock frequency
- Change name of the FPGA design
- Remove outdated docs
- Verilog linter warnings
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 2
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 14
- support for OpenPGP? HOT 1
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