CI about tillitis-key1

[secworks]

The "make verilator" target will be fixed. Not sure if we should run it as part of CI though. So "make", to build the whole FPGA including FW, and "make lint" should be in CI. IMHO.

[secworks]

I'll start looking into this. Possibly asking OlofK for help.

[mchack-work]

I pushed a container image built from contrib/Dockerfile to ghcr.io/tillitis/tkey-builder so it can be used by Github Actions. Not sure if we can keep it there since it's 2.3 GiB.

Also, see #56 for some podman targets including a podman-run-make which actually builds the bitstream using a podman container.

[quite]

I've added basic CI. On push to main and on PR it does:

• build all
• check fw C code fmt
• I also added spdx-ensure script like I did in the apps repo. But it is not enabled, as we have many files in hw/boards/ and hw/production_test/ that either need the SPDX tag, or should be marked in the script as not needing the tag.
• [ ] should also do make verilator, but it is currently broken @secworks

Also @secworks I see we have a make lint target that uses verilator for linting, but there are quite some lint_issues.txt that should be fixed before we can run it automatically (perhaps some are related to verilator build currently breaking)

[secworks]

Regarding the warnings in lint_issues. All but one relates to issues in the ice40 cell library, and ports not assigned by Yosys when instantiating the cells. This is external to our design. The final warning relates to PicoRV32 using both blocking and non-blocking assignments for the same signal. This is bad coding, but will break the CPU functionality. Since we instantiate the PicoRV32 as a component, I've decided to ignore it too.

[quite]

No we chose to not actually run verilator for now. And leave the spdx-ensure out for now.