Comments (3)
Ouch! Thanks!
from tillitis-key1.
icetime really don't like combinational loops. Need to check if one can ignore those paths.
Report for critical path:
loop-start at net_93660
t26053 (LocalMux) I -> O: 1.099 ns
inmux_24_27_97944_97979 (InMux) I -> O: 0.662 ns
lc40_24_27_5 (LogicCell40) in1 -> lcout: 1.232 ns
1000002.993 ns net_93660 (trng_inst.f[11])
t26052 (LocalMux) I -> O: 1.099 ns
inmux_24_27_97936_97949 (InMux) I -> O: 0.662 ns
lc40_24_27_0 (LogicCell40) in1 -> lcout: 1.232 ns
1000005.987 ns net_93655 (trng_inst.rosc_ctrl_logic.xor_f_SB_LUT4_O_I0[2])
odrv_24_27_93655_93688 (Odrv4) I -> O: 0.649 ns
t26058 (LocalMux) I -> O: 1.099 ns
inmux_24_29_98193_98260 (InMux) I -> O: 0.662 ns
1000008.397 ns net_98260 (trng_inst.rosc_ctrl_logic.xor_f_SB_LUT4_O_I0[2])
lc40_24_29_7 (LogicCell40) in0 [setup]: 1.060 ns
1000009.457 ns net_93908 (trng_inst.sample1_new[1])
Resolvable net names on path:
1000002.993 ns ..1000004.755 ns trng_inst.f[11]
1000005.987 ns ..1000008.397 ns trng_inst.rosc_ctrl_logic.xor_f_SB_LUT4_O_I0[2]
lcout -> trng_inst.sample1_new[1]
Total number of logic levels: 3
Total path delay: 1000009.46 ns (0.00 MHz)
// Checking 55.56 ns (18.00 MHz) clock constraint: FAILED.
from tillitis-key1.
@airskywater Do you have one of the TK1 dev kits we handed out on OSFC?
If not, please contact me and we'll send you a kit.
from tillitis-key1.
Related Issues (20)
- Clean up lint warnings. Again HOT 2
- Add context when sending device app HOT 1
- Run SPDX check in CI
- Update linter to Verilog-2005 HOT 2
- Add build of FPGA design with Icarus
- Add Icarus Verilog to tools installed HOT 2
- Try to remove all VERSION fields from cores
- Add more (security) code checkers to CI HOT 1
- Optimize FPGA design for clock frequency
- Change name of the FPGA design
- Remove outdated docs
- Verilog linter warnings
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 2
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 14
- support for OpenPGP? HOT 1
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from tillitis-key1.