Related Issues (20)
- Add a Verilog formatter
- Make testbenches self testing, and with correct exit code
- Idea: ability (but not enforced) to clear (or R/W) CDI HOT 4
- Improve community information about the project HOT 1
- Increase clock frequency of application_fpga HOT 3
- Clean up UDI and UDS implementation as well as udi_uds_patch program
- Add support for client based device reset HOT 15
- support for OpenPGP? HOT 1
- Rewrite code to reduce resource allocation HOT 1
- Update core local Makefiles to use Verilog-2005 for sim, linting
- Hardware support to access flash
- Signal to firmware not to load app from flash HOT 2
- FW: Optionally start app from flash
- CH552 fw: Support for different USB classes: CDC and HID HOT 2
- Support communication to different USB endpoints
- FIDO2 device app
- Change names of ADDR_RAM_ASLR and ADDR_RAM_SCRAMBLE HOT 1
- Device app to test hold touch HOT 1
- Remove possible redundant RAM clearing functionality HOT 2
- Remove possibly redundant randomized RAM scrambling during randomised RAM fill HOT 1
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