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thomasahle avatar thomasahle commented on June 1, 2024

There are two ways of doing this. Assume data is given in d nibbles:

       a0 a1 a2 ... ad <- Row of 4 * d bits
       b0 b1 b2 ... bd
       ...

Then we can use the normal QuickADC format:

       =====================
       a0 a1 b0 b1 ... h0 h1 <- 64 bits
       i0 i1       ... p0 p1 <- 64 bits
       =====================
       a2 a3 b2 b3 ... h2 h3 <- If using AVX we'll read these 128 bits
       i2 i3       ... p2 p3    together with the previous 128 bits, so we must have d % 4 = 0.
       =====================
       ...
       i(d-1) id   ... p(d-1) pd
       =====================
       q0 q1 r0 ...          <- Beginning of new New chunk
       ...
       =====================

In this case, AVX eating 256 bits at a time, will take the two rows

       =====================
       a0 a1 b0 b1 ... h0 h1
       i0 i1       ... p0 p1
       =====================
       a2 a3 b2 b3 ... h2 h3 
       i2 i3       ... p2 p3
       =====================

Meaning we need a dimension divisible by 4.
Alternatively, we could use the second channel to handle some more vectors

       =====================
       a0 a1 b0 b1 ... h0 h1
       i0 i1       ... p0 p1
       =====================
       q0 q1 r0 r1 ... x0 x1
       y0 y1       ... 
       =====================

Computing the distance to 32 vectors at a time, instead of 16 at a time.
QuickADC suggests the first approach, which has the advantage of using the same memory format, but I don't know exactly why it should be better.

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thomasahle avatar thomasahle commented on June 1, 2024

I added the first version of AVX in 95751ae.

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thomasahle avatar thomasahle commented on June 1, 2024

Do we have any issues with mixing SSE and AVX?
https://www.intel.com/content/dam/develop/external/us/en/documents/11mc12-avoiding-2bavx-sse-2btransition-2bpenalties-2brh-2bfinal-809104.pdf

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