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4-request-first-come-first-serve-arbiter

4 request first come first serve arbiter design using verilog HDL

arm-cpu

basic arm cpu without and with 5 stage pipelining

arm9-compatible-soft-cpu-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

cache-coherence-simulator

cachecoherence

Implementation of MI, MSI, MESI, MOSI, MOESI, and MOESIF protocols for a bus-bases broadcast system.

comp_arch_list

List of required readings for three-semester course in Computer Architecture at UCU (Principles of Computer Organization, Computer System Architecture, Operating Systems)

cyclic-redundancy-check

A cyclic redundancy check is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. Blocks of data entering these systems get a short check value attached, based on the remainder of a polynomial division of their contents.

dccsm

Directory-based cache coherence simulator

howto

introtodeeplearning

Lab Materials for MIT 6.S191: Introduction to Deep Learning

mesi-cache-coherence

moesi-cache-coherence

Multiprocessor cache coherence with MOESI protocol Simulator

reed-solomon_proof_of_concept

Proof of concept on how to implement the Reed Solomon class of error correcting codes in Python

reedsolomon_implement

Implementation of Reed-Solomon error correction

serdespy

Python library for SerDes modelling

sv_rnm

systemverilog-homework

SystemVerilog language-oriented exercises

vim

The official Vim repository

vimrc_customize

The ultimate vim distribution

viterby

Viterbi alorithm for IA Course