Comments (1)
Hi @coder-humbitious ,
Thank you for focusing on my AXI BFM !
Followings are answers for your questions.
Is it likely to work with iVerilog or Verilator or SV-Parser etc open-source Verilog simulators.
I think there are no OSS simulators supporting my AXI BFM because my AXI BFM is built on UVM (Universal Verification Methodology; industry standard platform to build testbenches written in SystemVerilog). To use my AXI BFM and UVM, commercial simulators, such as VCS and Xcelium are needed.
There are two ways to use simulators supporting UVM;
- Use EDA Playground. You can use the latest VCS without a fee on this side. But there are some limitations like run time, I think.
- Use the latest Vivado simulator. From version 2019.2, Vivado simulator supports UVM and I think you can use this simulator without a fee. However, I have not yet used this simulator so I don't know if my AXI BFM works with this simulator.
Will we able to use in an axi-switch verification environment...?
Maybe yes. I use my AXI BFM to verify my NoC fabric. You can refer the testbench for my NoC fabric to create your AXI switch. Following links are to the testbench and testcases implementations.
https://github.com/taichi-ishitani/tnoc/tree/master/env/axi_adapter
https://github.com/taichi-ishitani/tnoc/tree/master/test/axi_adapter
we are trying to read through and unwind them
You only have to read following source files because these are implementing user interface.
- Interface to connect DUT
- User interface to create stimulus and to get monitored transactions
- https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_item.svh
- https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_master_access_sequence.svh
- https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_master_write_sequence.svh
- https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_master_read_sequence.svh
- https://github.com/taichi-ishitani/tvip-axi/blob/master/src/tvip_axi_slave_default_sequence.svh
You're welcome to ask any questions !
from tvip-axi.
Related Issues (20)
- error on find vif failure HOT 11
- problem about sequencer HOT 2
- use TVIP-AXI as a component within in_agent HOT 1
- feature comparison to commercial VIPs HOT 1
- Error when elab with Vivado HOT 9
- tvip_axi_if.sv interface ports are better to be defined as logic instead of bit HOT 1
- Support Vivado simulator HOT 6
- NULL pointer dereference is observed after the reset in the middle HOT 4
- Another NULL pointer dereference after reset in the middle HOT 7
- Add support to drive W channel before AW HOT 7
- Not an issue but a general question
- Cadence Xcelium doesn't support variable substitution in if-condition HOT 4
- Support Veridi Protocol/Performance Analyzer
- Problem with On the Fly Reset HOT 5
- where is the "class tvip_delay_configuration" HOT 4
- axi_slave_sub_driver don't reset response_queue HOT 4
- Path example for replacing `uvm_do* macros HOT 1
- Mismatch issue HOT 8
- Problems with Vivado simulator HOT 4
- Add dsim simulator support
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