Comments (8)
The author of rv8 showed a neat technique to render histogram. See microsoft/mimalloc#529
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register usage histogram generated by rv8.
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I imported the LRU cache in this commit, so maybe we can display cache information in the profiling tool, such as cache size, cache hit rate, cache miss rate, cache hit times of a specific basic block, and the PC of the basic block.
For example,
Total cache access: xxx
Cache miss rate: xx.x%
Cache hit rate: xx.x%
Block PC | hit times | instruction in this block |
--------- | ------------ | ---------------------------- |
0x4 | xxx [xx.x%] | LW ADD BEQ |
.
.
.
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Check the way how mimalloc displays the internal information depending on environment variable MIMALLOC_VERBOSE
and MIMALLOC_SHOW_STATS
. Of course, the feature can be turned off via build-time flags.
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It is feasible to reuse existing map
for LRU cache implementation. See https://jaeyu.wordpress.com/2014/04/15/lru-cache-in-c/
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It is feasible to reuse existing
map
for LRU cache implementation. See https://jaeyu.wordpress.com/2014/04/15/lru-cache-in-c/
I try to integrate the existing map for LRU cache implementation, but the performance is worser than original version of LRU cache.
Performance of running CoreMarking
Mircoprocessor: Core i7-8700, Compiiler: gcc-12
- LRU cache with map: 464.427307 (Iterations/Sec)
- LRU cache without map: 978.822116 (Iterations/Sec)
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I imported the LRU cache in this commit,
The memory management concerns on basic block should appear in #105 .
Here, we still work on the statistics.
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rv64_emualtor comes with an ELF file instruction frequency analyzer. See rv_analyzer, which looks quite straightforward.
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Related Issues (20)
- CI: Generate Docker image with commit SHA1 HOT 2
- Compare with libriscv HOT 1
- Fix potential security issue in benchmark script
- jit: code generation tool should be aware of comments
- jit: Incomplete `muldivmod`
- Evaluate a hybrid approach for macro-operation fusion in both the decoding and execution stages
- Consolidate public header by integrating src/state.h HOT 1
- jit: Several errors are detected when running CoreMark
- Refactoring RISC-V emulation APIs for easier adoption and porting HOT 30
- jit: Enhance security by Control-Flow Integrity
- Comparing Interpreter performance with Wasm3
- Incorrect global/static float array initialization HOT 2
- Fail to build when ENABLE_EXT_C=0 ENABLE_JIT=1 HOT 1
- Accelerate ISA simulation by tiered JIT compilation HOT 13
- Assertion fail when running jit-bf with ENABLE_JIT=1
- jit: Implement register allocation for T1C HOT 2
- Provide minimal cross-platform GUI library HOT 2
- Incorrect basename generated by dynamic profiler
- jit: Assertion while running aes.elf HOT 2
- Potential uninitialized value read without initialization HOT 2
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