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2issp_v2

A 32-bit, two issue, super-scalar, MIPS processor that features an in-order scheduler and executes up to 22 instructions

2isspv3_ss

A static scheduler for my third implementation of a multiple issue superscalar processor based on the MIPS ISA

2wmips32_inorder

2-Way Superscalar processor based on the MIPS instruction Set

assemblerui

UI for demonstration of MIPS assembler

cachesim

Implementation of a trace based Cache simulator

cachesim_v2

Cache Simulator version 2

cmake-study

Repository containing my cmake studies

comprotocols

hardware implementation of communication protocol, SPI, UART, PCI

computerarithmetic

Repo containing HDL Implementations of Arithmetic Circuits

cpp

C++ works

cryptography

This repository consists of my Implementation of Cryptographic Algorithms in C++ and in Hardware

eda_study

Repository consisting of my study of EDA tools(ASIC Flow)

gf_workingbackwards

Implementation of GF Arithmetic Using std::bitset Library

gftranslator

Assembly Language Translator For Galois Field SIMD ASIP

gitig

inordescheduler_hw

Static scheduler for 2-issue(way/scalar), 5-stage pipeline MIPS processor implemented in Hardware

memorystudies

Contains my study of memories; design and hierachies

mips-32

Design of two 32-bit Microprocessor architectures based on the MIPS Instruction Set

mips-assembler

Assembler for built Processors

mips-compiler

Compiler

ponggame

Hardware based multiplayer pong game designed in VHDL and implemented on Spartan 3 FPGA

protocols

pythontuts

Repo for my python study!

training

source files from my eda training