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bessel

charlib

Open-source repository for a standard-cell library characterizer using complete open-source tools

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

ecen4243s24

Spring 2023 ecen4243 Computer Architecture Lab Material

ecen4303f23

Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University

globalfoundries-pdk-libs-gf180mcu_osu_sc

Digital standard cells for GF180MCU provided by Oklahoma State University.

hsca_s24

High-Speed Computer Arithmetic Spring 2024 at Oklahoma State University

openroad_new_platform_tutorial

osu-riscv

OSU Datapath/Control RV32 Single-Cycle and Pipelined Architecture in SV

osu-toy-sram

prefix_adders

Prefix adder generators for Verilog

random

Create C code to generate a bunch of random hex digits for use with SPICE decks

riscv-isa-manual

RISC-V Instruction Set Manual

sky130_cds

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

sky130rhbdlib

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

socc2018

Files associated with IEEE SOCC 2018 publication

springerbookarith04

These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"

stineje.github.io

tt04-submission-csam-2x2

Submission template for Tiny Tapeout 04

tt05-submission-julie

Submission template for Tiny Tapeout 05

xchiplogo

This is chiplogo a logo generator for VLSI chips.