Comments (1)
I've just pushed a fix for this, and also fixed up a few other cases I found by inspection.
from iverilog.
Related Issues (20)
- Support for "inside" statements HOT 2
- Incorrect uninitialised value and force/release behaviour when variable is partly driven by a continuous assignment
- Question on AMS support HOT 2
- Override parameters in top-level Verilog HOT 2
- Array depth defined with the num method of an enum where the variable name is identical to part of the enum instance name causes an error HOT 5
- unsigned port connection sign extends HOT 4
- fork..join_none inside automatic task fails assertion
- iverilog doesn't exit with an error code when an include file is missing. HOT 4
- Add support for `assert( l_c === 1'b0 );` syntax HOT 3
- Support implicit named port connections HOT 5
- Bug: accessing parameters by upward hierarchial name HOT 1
- Replication operator in literal array assignment pattern is not supported HOT 1
- vpi_put_value() at T0 is overridden HOT 2
- No error reported when an invalid or non-existent argument is passed to $bits
- vvp: array.cc:1561: void compile_array_alias(char*, char*, char*): Assertion `mem' failed.
- I think a signal goes up one clock cycle too early HOT 3
- Possible Data Transfer Anomaly HOT 8
- Nested generate statement not reported as syntax error
- ivl: logic_lpm.c:463: emit_nexus_port_signal: Assertion `! sig' failed.
- ivl: logic_lpm.c:485: find_local_signal: Assertion `! sig' failed. HOT 4
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from iverilog.