Comments (9)
Steve's never announced 10.2 as an official release. I did ask about this on the iverilog-devel mailing list a while back, but didn't get a reply. SourceForge is even more behind - it still shows 10.0 as the latest.
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If this was added it would only be as a specific warning type (.e.g. -Wfloating-nets) since you can have wires that look like they are dangling, but are actually driven by the VPI or possibly a force statement. It seems like this type of check is more appropriate in a linting tool not a simulation tool.
Would you want the same check for a register that is never assigned a value?
To properly do any of this would require a fairly complicated analysis of the full Verilog code and the VPI cannot be checked. To me this is probably more work than it is worth since we still have functionality specified in the standard to implement. This should really be added to the SourceForge feature request tracker since it is not a bug.
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Sounds reasonable. Anyway, what I am thinking about is that this could help avoid mistakes and oversights to some extend. It is also OK to have a standalone tool to check this kind of error, but I have no knowledge about such tools.
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For linting, check out --lint-only on verilator [1], which provides the following feedback on bug2.v, and is configurable.
$ verilator --lint-only -Wall bug2.v
%Warning-UNUSED: bug2.v:2: Signal is not used: a
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: bug2.v:2: Signal is not used: b
%Warning-UNDRIVEN: bug2.v:3: Signal is not driven: e
%Error: Exiting due to 3 warning(s)
%Error: Command Failed /usr/bin/verilator_bin --lint-only -Wall bug2.v
[1] http://www.veripool.org/wiki/verilator
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I actually have an idea how to tackle this, so I'll take a crack at it.
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I've pushed into git master support for the -Wfloating-nets flag, which does pretty much exactly what is requested here.
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This support was added in commit 8f095f1. This feature never made it to v10.2 (I haven't looked at older versions)
See: https://github.com/steveicarus/iverilog/blob/v10_2/driver/main.c#L495-L586
Can I ask what happened to this feature? Seems useful and (was) listed on the Wiki, so it appeared to be a feature available in the latest release.
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The latest release is v10.1. If/when there is a v10.2 release, it will be a maintenance release based on the v10 branch. Normally new features aren't backported to the stable branch, so as the Wiki says, this feature will become available in v11. If you want to use it now, you need to checkout and build from the master branch.
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Ah okay. That makes more sense. Apologies for my failure to read the Wiki correctly/thoroughly.
Not that it matters, but it sure seems like there is a 10.2 release. I see it both here on Github and in the FTP server. Maybe this is an "unreleased" release?
Thanks again for your clarification on the -Wfloating-nets
option. I'll try it out in master.
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Related Issues (20)
- Override parameters in top-level Verilog HOT 2
- Array depth defined with the num method of an enum where the variable name is identical to part of the enum instance name causes an error HOT 5
- unsigned port connection sign extends HOT 4
- fork..join_none inside automatic task fails assertion
- iverilog doesn't exit with an error code when an include file is missing. HOT 4
- Add support for `assert( l_c === 1'b0 );` syntax HOT 3
- Support implicit named port connections HOT 5
- Bug: accessing parameters by upward hierarchial name HOT 1
- Replication operator in literal array assignment pattern is not supported HOT 1
- vpi_put_value() at T0 is overridden HOT 2
- No error reported when an invalid or non-existent argument is passed to $bits
- vvp: array.cc:1561: void compile_array_alias(char*, char*, char*): Assertion `mem' failed.
- I think a signal goes up one clock cycle too early HOT 3
- Possible Data Transfer Anomaly HOT 8
- Nested generate statement not reported as syntax error
- ivl: logic_lpm.c:463: emit_nexus_port_signal: Assertion `! sig' failed.
- ivl: logic_lpm.c:485: find_local_signal: Assertion `! sig' failed. HOT 4
- Delayed transmission from tranif0/tranif1 primitives HOT 3
- Arrays can't be used in sensitivity lists HOT 6
- Clock of register is out of sync between RTL vs Yosys genereted netlist HOT 2
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