Can't infer width of Payload about spinalhdl

[Dolu1990]

Hi,

Sometime, scala has some limitation / restrictions with the range of implicits and need a bit of help XD

Here is one workaround :
switch(apply(OPCODE)) { //decode.Area.apply

Another one :
switch[Bits](OPCODE) {

Interestingly if I do OPCODE.asBits in a bit less mimized version of my design I get the metals environment to spit out interesting errors:

I tried, but can't reproduce that issue, it may be related to something else ?

Also i just tried :

    val decode = CtrlLink()
    val BOOL_PAYLOAD = Payload(Bool())
    val decoder = new decode.Area {
      val a = BOOL_PAYLOAD ? B"1" | B"0"
      val b = (BOOL_PAYLOAD === True) ? B"1" | B"0"
      val c = (B(BOOL_PAYLOAD) === B"1") ? B"1" | B"0"
      val d = (BOOL_PAYLOAD.asBits === B"1") ? B"1" | B"0"
      val e = Bits(1 bit)
      when(BOOL_PAYLOAD) {
        e := B"1"
      }.otherwise {
        e := B"0"
      }
    }
    Builder(decode)

They all work for me

In your example i think the issue is that you aren't in a "Node" context (new decode.Area)

So, the pipeline API has no "Node" to extract the payload from.
Payload(xxx) is realy for pipelining things.

Right when VHDL got on my nerves with its verbosity

<3 Pain pain pain <3

[andreasWallner]

@NikLeberg
For you last example, the issue is that you build the pipeline before you add the hardware into it.
(Your call to Builder(...) happens before the actual content of the pipeline is instantiated).

After fixing that we have to also connect inputs/outputs, otherwise all the HW gets optimized away and we might miss some issues. It works as expected like this (just a quick fix, not "nice" code):

case class Pipes() extends Area {
  val decode = CtrlLink()

  val IR = Payload(Bits(32 bits))
  val OPCODE = Payload(Bits(7 bits))
  val RD = Payload(UInt(4 bits))
}

case class DecodeOps(pipes: Pipes) {
  import pipes._

  val decoder = new decode.Area {
    OPCODE := IR(6 downto 0)
    RD := U(IR(10 downto 7))
  }
}

case class Bug() extends Component {
  val io = new Bundle {
    val ir = in port Bits(32 bit)
    val rd = out port UInt(4 bits)
    val opcode = out port Bits(7 bits)
  }
  val pipes = Pipes()
  val decodeOps = DecodeOps(pipes)

  pipes.decode(pipes.IR) := io.ir
  io.rd := pipes.decode.down(pipes.RD)
  io.opcode := pipes.decode.down(pipes.OPCODE)

  Builder(pipes.decode)
}

object BugTop extends App {
  SpinalConfig().generateVhdl{Bug()}.printPruned()
}

We should have a look whether we can generate a separate error message in this case - the current one is just from the fallout and is an aftereffect.

OT: In most cases you should place the Payloads into a companion object, not into the case class - that way you don't have different objects for every instance which can become really hard to reference down the line (since you need an instance to refer to them, the global singleton does not suffice).

[Dolu1990]

Hi,

I found one bug in the SpinalHDL library which was preventing width inferation on the very first signal created (if created by the pipelining API)

Here is the fix :
a4baf0d

It may fix your issue aswell.

[NikLeberg]

In a similar fashion.. why do none of these work?

case class BoolPayload() extends Area {
  val BOOL_PAYLOAD = Payload(Bool())
  val a = BOOL_PAYLOAD ? B"1" | B"0"
  val b = (BOOL_PAYLOAD === True) ? B"1" | B"0"
  val c = (B(BOOL_PAYLOAD) === B"1") ? B"1" | B"0"
  val d = (BOOL_PAYLOAD.asBits === B"1") ? B"1" | B"0"
  val e = Bits(1 bit)
  when(BOOL_PAYLOAD) {
    e := B"1"
  }.otherwise {
    e := B"0"
  }
}

[NikLeberg]

Hi there @Dolu1990
Thank you so much for the immediate response... although it helped a bit to use apply(...) I still encountered strange errors. It took some time to come up with a small example that behaves the same as the while design:

package curlyrv

import spinal.core._
import spinal.lib._
import spinal.lib.misc.pipeline._

import scala.collection.mutable.ArrayBuffer

case class Pipes() extends Area {
  val decode = CtrlLink()

  val IR = Payload(Bits(32 bits))
  val OPCODE = Payload(Bits(7 bits))
  val RD = Payload(UInt(5 bits))

  Builder(decode)
}

case class DecodeOps(pipes: Pipes) {
  import pipes._

  val decoder = new decode.Area {
    OPCODE := IR(6 downto 0)
    RD := U(IR(11 downto 7))
  }
}

case class Bug() extends Component {
  val pipes = Pipes()
  val decodeOps = DecodeOps(pipes)
}

object BugTop extends App {
  Config.spinal.generateVhdl(Bug()).printPruned()
}

The compile fails with error Static bits extraction (11 downto 7) is outside the range (-2 downto 0) of (toplevel/pipes_decode_down_IR : Bits[32 bits]) which I find very confusing. It says that the valid range is -2 downto 0 which is weird by itself, and then continues to say that it is 32 bits which is correct but should have a range of 31 downto 0 right?

What am I missing?

Full output of `sbt runMain curlyrv.BugTop`

[info] compiling 1 Scala source to /workspaces/curly-engine/target/scala-2.12/classes ...
[info] running (fork) curlyrv.BugTop 
[info] [Runtime] SpinalHDL v1.10.1    git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
[info] [Runtime] JVM max memory : 1984.0MiB
[info] [Runtime] Current date : 2024.05.18 07:10:53
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 0.318 : Checks and transforms
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (2 errors).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 0.446 : Elaborate components
[info] [Progress] at 0.457 : Checks and transforms
[error] Exception in thread "main" spinal.core.SpinalExit: 
[error]  Error detected in phase PhaseNormalizeNodeInputs
[error] ********************************************************************************
[error] ********************************************************************************
[error] Static bits extraction (11 downto 7) is outside the range (-2 downto 0) of (toplevel/pipes_decode_down_IR :  Bits[32 bits]) at
[error]     curlyrv.DecodeOps$$anon$1.<init>(Bug.scala:26)
[error]     curlyrv.DecodeOps.<init>(Bug.scala:24)
[error]     curlyrv.Bug.<init>(Bug.scala:32)
[error]     curlyrv.BugTop$.$anonfun$new$1(Bug.scala:36)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Design's errors are listed above.
[error] SpinalHDL compiler exit stack : 
[error]         at spinal.core.SpinalExit$.apply(Misc.scala:455)
[error]         at spinal.core.SpinalError$.apply(Misc.scala:510)
[error]         at spinal.core.internals.PhaseContext.checkPendingErrors(Phase.scala:177)
[error]         at spinal.core.internals.PhaseContext.doPhase(Phase.scala:193)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6(Phase.scala:2799)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6$adapted(Phase.scala:2797)
[error]         at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error]         at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$1(Phase.scala:2797)
[error]         at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:71)
[error]         at spinal.core.internals.SpinalVhdlBoot$.singleShot(Phase.scala:2732)
[error]         at spinal.core.internals.SpinalVhdlBoot$.apply(Phase.scala:2727)
[error]         at spinal.core.Spinal$.apply(Spinal.scala:412)
[error]         at spinal.core.SpinalConfig.generateVhdl(Spinal.scala:178)
[error]         at curlyrv.BugTop$.delayedEndpoint$curlyrv$BugTop$1(Bug.scala:36)
[error]         at curlyrv.BugTop$delayedInit$body.apply(Bug.scala:35)
[error]         at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error]         at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error]         at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error]         at scala.collection.immutable.List.foreach(List.scala:431)
[error]         at scala.App.main(App.scala:80)
[error]         at scala.App.main$(App.scala:78)
[error]         at curlyrv.BugTop$.main(Bug.scala:35)
[error]         at curlyrv.BugTop.main(Bug.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 2 s, completed May 18, 2024, 7:10:54 AM

[NikLeberg]

BTW if I rewrite it as:

val ir = U(IR)
RD := ir(11 downto 7)

The error becomes:

• Can't infer width on curlyrv.DecodeOps$$anon$1.<init>(Bug.scala:25) and
• Negative width on (Bits -> UInt of -1 bits) at curlyrv.DecodeOps$$anon$1.<init>(Bug.scala:25).

Full output of `sbt runMain curlyrv.BugTop`

[info] compiling 1 Scala source to /workspaces/curly-engine/target/scala-2.12/classes ...
[info] running (fork) curlyrv.BugTop 
[info] [Runtime] SpinalHDL v1.10.1    git head : 2527c7c6b0fb0f95e5e1a5722a0be732b364ce43
[info] [Runtime] JVM max memory : 1984.0MiB
[info] [Runtime] Current date : 2024.05.18 07:23:41
[info] [Progress] at 0.000 : Elaborate components
[info] [Progress] at 0.324 : Checks and transforms
[info] **********************************************************************************************
[info] [Warning] Elaboration failed (2 errors).
[info]           Spinal will restart with scala trace to help you to find the problem.
[info] **********************************************************************************************
[info] [Progress] at 0.523 : Elaborate components
[info] [Progress] at 0.541 : Checks and transforms
[error] Exception in thread "main" spinal.core.SpinalExit: 
[error]  Can't infer width on     curlyrv.DecodeOps$$anon$1.<init>(Bug.scala:25)
[error]     curlyrv.DecodeOps.<init>(Bug.scala:23)
[error]     curlyrv.Bug.<init>(Bug.scala:32)
[error]     curlyrv.BugTop$.$anonfun$new$1(Bug.scala:36)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] Negative width on (Bits -> UInt of -1 bits) at     curlyrv.DecodeOps$$anon$1.<init>(Bug.scala:25)
[error]     curlyrv.DecodeOps.<init>(Bug.scala:23)
[error]     curlyrv.Bug.<init>(Bug.scala:32)
[error]     curlyrv.BugTop$.$anonfun$new$1(Bug.scala:36)
[error]     spinal.sim.JvmThread.run(SimManager.scala:51)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Design's errors are listed above.
[error] SpinalHDL compiler exit stack : 
[error]         at spinal.core.SpinalExit$.apply(Misc.scala:455)
[error]         at spinal.core.SpinalError$.apply(Misc.scala:515)
[error]         at spinal.core.internals.PhaseInferWidth.impl(Phase.scala:1469)
[error]         at spinal.core.internals.PhaseContext.doPhase(Phase.scala:183)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6(Phase.scala:2799)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6$adapted(Phase.scala:2797)
[error]         at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
[error]         at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
[error]         at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
[error]         at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$1(Phase.scala:2797)
[error]         at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:71)
[error]         at spinal.core.internals.SpinalVhdlBoot$.singleShot(Phase.scala:2732)
[error]         at spinal.core.internals.SpinalVhdlBoot$.apply(Phase.scala:2727)
[error]         at spinal.core.Spinal$.apply(Spinal.scala:412)
[error]         at spinal.core.SpinalConfig.generateVhdl(Spinal.scala:178)
[error]         at curlyrv.BugTop$.delayedEndpoint$curlyrv$BugTop$1(Bug.scala:36)
[error]         at curlyrv.BugTop$delayedInit$body.apply(Bug.scala:35)
[error]         at scala.Function0.apply$mcV$sp(Function0.scala:39)
[error]         at scala.Function0.apply$mcV$sp$(Function0.scala:39)
[error]         at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
[error]         at scala.App.$anonfun$main$1$adapted(App.scala:80)
[error]         at scala.collection.immutable.List.foreach(List.scala:431)
[error]         at scala.App.main(App.scala:80)
[error]         at scala.App.main$(App.scala:78)
[error]         at curlyrv.BugTop$.main(Bug.scala:35)
[error]         at curlyrv.BugTop.main(Bug.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 2 s, completed May 18, 2024, 7:23:41 AM

[NikLeberg]

Hi @Dolu1990

Awesome! If I compile my example from above (with the fix of calling Builder(decode) after defining the logic) it now does not throw the width infer error and compiles with success!
Conversely if I go back to the latest released version 1.10.1 it fails with the mentioned error.
Interestingly, if I do what @andreasWallner suggested and prevent optimization by routing the payload to an IO bundle, then the error disappears even on 1.10.1.

Thank you both for your work and suggestions. For me this issue is fixed and I'm closing it. Feel free to reopen if you want to track:

We should have a look whether we can generate a separate error message in this case - the current one is just from the fallout and is an aftereffect.

Thanks, Nik