Sinn's Projects
This project implements a convolution kernel based on vivado HLS on zcu104
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
AiLearning: 机器学习 - MachineLearning - ML、深度学习 - DeepLearning - DL、自然语言处理 NLP
A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
《CPU设计实战》学习记录及代码
Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
GM-PHD filter in target tracking
Machine learning on FPGAs using HLS
:fish::fish::fish: 机器学习面试复习资源
MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
MAERI public release
An analytical cost model evaluating DNN mappings (dataflows and tiling).
A NPU designed by Vivado HLS
MIPS CPU emulator
RISC-V CPU simulator for education purposes
UCSD CSE 237D Spring '20 Course Project
Rethinking the Value of Network Pruning (Pytorch) (ICLR 2019)
Siam R-CNN two-stage re-detector for visual object tracking
Config files for my GitHub profile.
iSmart3 https://github.com/TomG008/SkyNet
FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)
HLS-based Graph Processing Framework on FPGAs
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Open deep learning compiler stack for cpu, gpu and specialized accelerators
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.