Comments (1)
The L2 cache can be configured as a cache or as on chip memory (LIM), or as a mixture. The zsbl loads the fsbl into LIM. It can't use DRAM as the fsbl needs to run first to initialize the DRAM. There is info on the L2 Cache and LIM in the FU540 manual. There is also a chapter on the boot process.
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Related Issues (13)
- This version did not do the full linux boot. HOT 2
- what does unimp a0 a1 mean? HOT 5
- undefined reference to `__libc_detect_null' HOT 13
- device tree error HOT 3
- Merging build-fixes branch to master? HOT 3
- Why is zsbl/ux00_zsbl.dts different from fsbl/ux00_zsbl.dts
- Fails to build with clang
- location of ROM binary? HOT 8
- a memcpy bug(possibly) HOT 2
- Bootrom challenge notes HOT 3
- Your license template needs finished
- how to use fsbl.bin in HighFive Unleashed board ? HOT 10
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