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Hi, I am Sarthak 👋

I am Sarthak Chakraborty, pursuing PhD in Computer Science at University of Illinois Urbana-Champaign (UIUC). Prior to this, I was working as a Research Associate 2 at the Adobe Research, Bangalore. I was in the Systems and Insights group. I graduated from IIT Kharagpur holding a Dual Degree (B.Tech + M.Tech Integrated) from the Department of Computer Science and Engineering. I am interested in the fields of ML for Systems, Distributed Systems, System Design, Deep Learning and Operating Systems.

Tools and Technologies

Sarthak Chakraborty's Projects

acto icon acto

Push-Button End-to-End Testing of Kubernetes Operators and Controllers

causil icon causil

CausIL is an approach to estimate the causal graph for a cloud microservice system, where the nodes are the service-specific metrics while edges indicate causal dependency among the metrics. The approach considers metric variations for all the instances deployed in the system to build the causal graph and can account for auto-scaling decisions.

distributed-collaborative-editor icon distributed-collaborative-editor

Distributed Collaborative Editor including Passive Replication and Fault Tolerance implemented as a term project for the course Distributed Systems (CS60002) [IIT Kgp]

distributed_systems icon distributed_systems

[CS 425][UIUC] Course Assignments for Distributed Systems Class in UIUC. Implemented a miniature version of Hadoop capable of running Map-Reduce tasks

esro icon esro

This is the official repository for the code used in the paper ESRO: Experience Assisted Service Reliability against Outages (ASE 2023).

fedbn icon fedbn

[ICLR'21] FedBN: Federated Learning on Non-IID Features via Local Batch Normalization

fl-crosschain icon fl-crosschain

It is the official repository for the paper Proof of Federated Training: Accountable Cross-Network Model Training and Inference, published at IEEE ICBC 2022

hcne icon hcne

A Hierarchical Clustering Approach for Network Embedding

kgprisc icon kgprisc

Single Cycle CPU design (RISC architecture) developed in Xilinx ISE 14.7 using Verilog

minssl icon minssl

Minimally Supervised Semi-Supervised Learning

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