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ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

amba_axi_ahb_apb

AMBA bus lecture material

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

caravel

deep_learning_blocks

DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.

python

All Algorithms implemented in Python

router-1-3

verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL

vsdpllsoc