roalogic Goto Github PK
Name: Roa Logic BV
Type: Organization
Blog: www.roalogic.com
Name: Roa Logic BV
Type: Organization
Blog: www.roalogic.com
8b10b encoder/decoder
Universal Advanced JTAG Debug Interface
Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
AHB module that always generates an error response
AHB3-Lite Interconnect
Multi-Technology RAM with AHB3Lite interface
Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
AHB3 Lite SDRAM Controller
RISC-V compliant Timer IP
General Purpose IO with APB4 interface
APB4 Multiplexor
16550 UART with APB4 Interface
APB module that always generates an error response
Hamming ECC Encoder and Decoder to protect memories
Generic memory implementations
OpenOCD clone for porting RoaLogic Debuggers
Platform Level Interrupt Controller
RISC-V Instruction Set Manual
Eclipse Plugin for RISC-V GNU Toolchain
Roa Logic Theme for GitHub Pages
Roa Logic GitHub Pages Site (Top Level)
RISC-V CPU Core
C demo code to use with the rv_soc
Roa Logic RISC-V SoC
Universal JTAG TAP Controller
Collection of C++ classes to create Verilator Testbenches
VGA LCD Core (OpenCores)
VIM Syntax file for SystemVerilog
Yosys Open SYnthesis Suite
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