Comments (6)
Linux uses the standard page table described in the privileged spec. How TLBs work is a question for your chip vendor.
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So TLB filling is done by hardware. Is it?
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It can be done by hardware or software. It is not done by Linux.
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Few doubts regarding Page table
Is it optional to implement hardware page walker?
If it is can be done by software, up to what extent OS will do?
Means decision of which page to replace will done by OS?
Is OS looking for multi-level paging?
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The bug tracker is not a forum and this isn't even a related repository.
Page table walker is not in the OS. If it's software, it's non-OS software (e.g. M-mode trap handled in a M-mode monitor program that runs above Linux). Why do you keep asking? What are you trying to achieve?
As far as any OS knows, page tables are walked automatically.
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I'm closing this: like @sorear said this isn't the right place to ask this question. [email protected] might be a better place to do it.
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Related Issues (20)
- Build fails with lack of auto-generated headers HOT 6
- what branch or tag is suitable for riscv-qemu HOT 2
- Documentation/riscv HOT 1
- CONFIG_NO_HZ=y possibly broken HOT 8
- WARNING: CPU: 0 PID: 0 at drivers/irqchip/irq-riscv-intc.c:158 irq_enable+0x32/0x58 HOT 4
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- Asking for help! Error in execution of compiled : $Top/riscv-tools/lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld:unsupported -shared HOT 3
- linker issue undefined reference to __lshrti3 HOT 9
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- icache not flushed correctly HOT 8
- riscv-linux compile issue in branch riscv-all HOT 1
- Stopping lo interface Oops HOT 2
- unknown architecture riscv. HOT 1
- GPIO & PWM spec for Unleashed HOT 2
- perf_tools support
- What instruction sets do I need to run Linux on my own risc-v CPU? HOT 7
- Any plan for upstreaming DMA32? HOT 2
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