riscv-spec Goto Github PK

riscv-acpi-ffh

The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification

riscv-aia

riscv-asm-manual

RISC-V Assembly Programmer's Manual

riscv-bfloat16

riscv-bitmanip

Working draft of the proposed RISC-V Bitmanipulation extension

riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

riscv-cmos

riscv-code-size-reduction

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

riscv-count-overflow

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv-iommu

Non-ISA IOMMU specification developed by the IOMMU TG.

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-isac

riscv-j-extension

Working Draft of the RISC-V J Extension Specification

riscv-matrix-extension-spec

A matrix extension proposal for AI applications under RISC-V architecture

riscv-opcodes

RISC-V Opcodes

riscv-p-spec

RISC-V Packed SIMD Extension

riscv-plic-spec

PLIC Specification

riscv-profiles

RISC-V Architecture Profiles

riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

riscv-semihosting-spec

riscv-smbios

RISC-V SMBIOS Type 44 Spec

riscv-spmp

The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.

riscv-ssqosid

This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.

riscv-ssrastraps

The RAS exception and interrupts extension (Ssrastraps) defines standard local interrupt numbers and exception-cause codes for reporting errors detected by RAS functions in the system.

riscv-state-enable

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.