Comments (2)
I believe the error in your screenshot is due to the fact that you haven't specified the configuration file for the dataset. Even if you're using the "randomize" parameter, you still need to specify the dataset.
Furthermore, due to the limitations of the configuration (as stated below), it seems that fadd.d only supports flen=64. In fact, that's the case. You may need to specify flen as 64.
fadd.d:
sig:
stride: 2
sz: 'SIGALIGN'
val:
stride: 2
sz: 'FLEN/8'
val_template: "'NAN_BOXED($val,$width,FLEN)'"
load_instr: "FLREG"
xlen: [32,64]
isa:
- IFD_Zicsr
flen: [64]
rm_val_data: '[7,0,1,2,3,4]'
fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
std_op:
formattype: 'rformat'
rs1_op_data: *all_fregs
rs2_op_data: *all_fregs
rd_op_data: *all_fregs
template: |-
Additionally, when executing the instruction, you may encounter the issue related to #102 . Although I'm not entirely sure what issues are involved in the merge, if you want to attempt generating a test file, you can modify it based on #102 first.
And you can try:
riscv-ctg --base-isa rv64i --flen 32 --cgf ./sample_cgfs/dataset.cgf --cgf ./sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf -d ./tests/ --randomize -v debug -p2
to generate test . It takes time , however
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@Abdulwadoodd , @MuhammadHammad001 , @ahadali-10x can you please look at this error?
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Related Issues (20)
- Variable 'xlenlim' not defined in abstract_comb of a few bitmanip instructions HOT 1
- Whether support for Vector ISA is planned? HOT 2
- Quad Precision Mnemonics Support Error for riscv-ctg HOT 1
- Rename sample_cgfs
- Randomised tests are not reproducible HOT 1
- Test generation for CSR testing. HOT 2
- Cleanup for Floating point extensions. HOT 20
- Necessary corner cases and tests for `FD` extensions. HOT 1
- Mismatch between hex and decimal values in the comments section of generated .S file HOT 7
- Adding csr instruction support in riscv-ctg to create coverpoints for riscof HOT 2
- Generate fld, fsd, fsw, flw tests report error HOT 4
- When `xlen<flen`, some registeres are reserved, this has to be addressed as part of all .d tests HOT 1
- Can riscv-ctg support vector ISA? HOT 2
- Key 'label' is not part of the dictionary key at this part of execution HOT 1
- Missing documentation for Instr Attributes HOT 1
- Issues Generating Test Cases with riscv-ctg-0.11.0 HOT 1
- Problem while generating floating point tests HOT 2
- For RV32I_K generator.py report error HOT 1
- How to generate tests for RV64D and RV64F using riscv-ctg? HOT 1
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