Latency with MappedMemory about renode

[mateusz-holenko]

Hi @slosar, thanks for asking the question.

Renode simulations operate based on fully-controlled virtual time flow which allows us to obtain reproducible results and recreate scenarios where timing of events is important from the perspective of a simulated application.

Having said that, at the CPU level we operate on a simplified model where we assume that on average execution of each instruction takes the same amount of time. The performance of the CPU itself (the number of executed instructions per virtual second) can be controlled with the PerformanceInMIPS parameter.

For simulation performance reasons accesses to MappedMemory are optimized and executed as pointer operations directly at CPU level to avoid the necessity of executing C# layer.

To assess performance of your system taking into account memory accesses, you might use the post-mortem analysis of the execution traces. Please take a look at https://antmicro.com/blog/2023/07/risc-v-co-design-using-trace-based-simulation-with-renode-and-tbm/ and https://antmicro.com/blog/2022/09/execution-tracing-in-renode/.

Of course extending current CPU model with the notion of long-running instructions is technically possible, but would require some design and implementation work.

[jzee]

@mateusz-holenko - that's interesting. In a fit of trying to understand what the assumption behind the average execution time is, I simulated an STM32F4 and ran 1M loops of 100 asm("nop") at PerformanceInMIPS = 168 . Then I compared this to the runtime on the actual STM32F4 discovery board, which is clocked at 168MHz.

It turns out that the HW board performs only marginally better than the Renode simulation (613.1ms on HW vs 625ms on renode).

This seems to indicate that the average execution time that renode assumes for a Cortex-M4 is only very slightly (~2%) higher than 1. Is that an expected result? Can I tweak that number somewhere?

[slosar]

A somewhat related question, would it be possible to implement something like that as a python peripheral. Can python peripheral force "wait" cycles to the CPU? In practice any modern system does not use a constant time to fetch contents of memory location, but any effects of cache, etc should still be quite straightforward to deterministically simulate.

[slosar]

It turns out that the HW board performs only marginally better than the Renode simulation (613.1ms on HW vs 625ms on renode).

I think any NOP takes exactly one cycle to execute. What you are seeing is almost certainly time "quantization" I think. Have you tried taking 10M loops vs 1M and see if the discrepancy changes?