Add Wishbone bus support to VerilatorPlugin about renode

[mithro]

+1

[mateusz-holenko]

It’s indeed a good idea - in fact we have already internally planned to add this support in the future. We don’t have, however, any specific roadmap planned for it at the moment.

As a workaround you can always include a Wishbone-to-AXI bridge in your Verilator simulation so that you talk to Renode over the currently supported AXI4-Lite.

[mithro]

I would say that wishbone is a high priority for me.

[mateusz-holenko]

70ce00f adds Wishbone bus support to Verilator Plugin.

We are currently working on a demo for this feature.

[mateusz-holenko]

We have published a demo of LiteX/VexRiscv platform with verilated LiteUART (using wishbone bus) in Renode: a711027 .

There are also commits adding support for interrupts from the verilated peripheral.

[mateusz-holenko]

We published sources of the demo of LiteX/VexRiscv platform with verilated LiteUART using wishbone bus at https://github.com/antmicro/renode-verilator-integration/tree/master/samples/liteuart.

[mateusz-holenko]

@xobs, @mithro: If you don't have any additional insights/comments, I guess we can close this issue?

[xobs]

@mateusz-holenko Sorry to be obtuse, but how was top.v generated? Was it built using the Sim platform? What did you do to expose the Wishbone bus out the top? Similar to what I did with spibone (https://github.com/xobs/spibone/blob/master/sim/generate-verilog.py)?

[mateusz-holenko]

@xobs We generated the top.v file using the script from LiteX: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py with ./tools/litex_gen.py --with-uart.
It uses the wishbone bus by default, but can be changed to axi as well.

Exposing the bus is done in https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py#L99, which uses additional functions we've recently added: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L73 and https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L80.

[PiotrZierhoffer]

I think we can close this one. @xobs if you have any more questions/inquiries about this, please let us know