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jeremy-baker avatar jeremy-baker commented on August 28, 2024

I presume you are using the RA2L1? Which version of the FSP?

This code works for me on the EK-RA2L1 using FSP 2.3.0 to set and clear GPIO P5_01 :-

R_PMISC->PWPR = 0x00;
R_PMISC->PWPR = 0x40;

R_PFS->PORT[5].PIN[01].PmnPFS_b.PMR = 0; //GPIO

R_PFS->PORT[5].PIN[01].PmnPFS_b.PDR = 1; //Set Pin as output

R_PFS->PORT[5].PIN[01].PmnPFS_b.PODR = 1; //P5_01 HIgh using PFS

R_PFS->PORT[5].PIN[01].PmnPFS_b.PODR = 0; //P5_01 Low using PFS

R_PORT5->PCNTR3 = 0x00 | (1 << 1); //P5_01 Set using PCNTR3

R_PORT5->PCNTR3 = 0x00 | ((1 << 1) << 16); //P5_01 Reset PCNTR3

R_PORT5->POSR   = 0x00 | (1 << 1); //P5_01 Set using PCNTR3

R_PORT5->PORR   = 0x00 | (1 << 1); //P5_01 Reset PCNTR3

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alexrayne avatar alexrayne commented on August 28, 2024
R_PORT5->PCNTR3 = 0x00 | (1 << 1); //P5_01 Set using PCNTR3

R_PORT5->PCNTR3 = 0x00 | ((1 << 1) << 16); //P5_01 Reset PCNTR3

i guess that this lines are used 16bit access too. do you check disassembler?

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alexrayne avatar alexrayne commented on August 28, 2024

This code works for me on the EK-RA2L1 using FSP 2.3.0 to set and clear GPIO P5_01 :

32bit access not works even from IO-access view at debugger session. But POSR/PORR works well

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jeremy-baker avatar jeremy-baker commented on August 28, 2024

The write to the PCNTR3 register is a 32 bit access (STR instruction) :-

image

The access to the POSR/PORR is a 16 bit access (STRH instruction) :-

image

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