Related Issues (17)
- It would be nice to reference components by their name
- Easier way to set up Port and Generic maps
- Need ability to convert signals on sub-module inputs
- Add ability to choose between vhd and vhdl file extensions
- SignalInfo generates incorrect code
- SignalInfo places order of preclock signal and type incorrectly
- Type and Subtypes are generated incorrectly
- Header info should be alphabetized
- Make SimplifiedGenericInfo and SimplifiedPortInfo support IComparable
- Add "Structure" to ArchitecturalType
- Add the ability to specify section header formatting.
- Add setting to determine whether closing name is added or not HOT 1
- Create a setting to specify whether spaces should be placed after keywords HOT 1
- Descriptions should wrap to their beginning mark.
- Add support for records
- Components aren't currently added for sub-modules in generates.
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