Magma is main, verilog is linked about linker

[leonardt]

Can you clarify what you want an example of? If you mean an example of using a templated verilog file, see the second cell in this notebook: https://github.com/phanrahan/magma/blob/master/notebooks/tutorial/Verilog.ipynb

We could add a similar interface which is DeclareFromCoreIRVerilogGenerator('generator_name', **params) which returns a magma circuit declaration with the matching ports/types. Then this could be compiled to CoreIR just in terms of the declaration which I think should just work.

The DeclareFromCoreIRVerilogGenerator could pass the generator reference and parameters to a coreir tool to get the coreir declaration for the generated module, which we could then parse using pycoreir to generate a magma declaration.

[rdaly525]

Yeah, that was what I meant.

Since ideally magma does not need to know that library was from verilog, maybe something more generic like "DeclareFromExtern" or something along those lines. Ideally you just have to write one import function that will work independent of what langauge the libraries were written in.

[leonardt]

Yea that makes sense, I like the notion of an extern. The most explicit/verbose name would be DeclareFromExternGenerator, can brainstorm with a more concise name but I'll go with that for now.