RP1 (Pi 5) DSI issue with 4 lanes about linux

[njhollinghurst]

Been doing some experiments with the 7" display (even though it uses only 1 lane)...

When DPI rate is imprecisely derived from the 200MHz core clock: the screen works but flickers, with a horizontal jitter.

DSI Host has the option to inhibit returning to LP mode during HBP, which may guarantee that the offset between HSYNC and data will be a fixed number of MIPI clocks. Unfortunately that doesn't cure the jitter!*

There is a limited palette of pixel rates for which we can derive DPI rate from the core clock and DSI from the MIPI PLL, in an exact ratio. With one lane at 24bpp, 28.571Mpix/s is one such rate, and it displays perfectly.** With 4 lanes there would be about 25 such rates in the range 13.333Mpix/s to 160Mpix/s.

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*I guess the bridge chip expects the line period to be uniform, or perhaps an exact multiple of its own re-generated (divided) DPI clock. Let's hope other displays are less fussy.

**it doesn't bear too much thinking about how this displays without jitter, since the phase relationship between the two clocks is undefined.