Comments (1)
因为已经隔了好久,我已经想不起来当初的思路了。
粗略看了一下,感觉我的思路应该没问题。问题在于Verilog怎么处理小数。我印象中我曾经是考虑过这个问题的。
比如 DATAWIDTH 是7,FILTERWIDTH 是3,STRIDEWIDTH 是2,正确的结果应该是3。
按照我的计算方式的话就是2.5,如果处理过后是3的话,就是对的,处理过后是2的话就是错的。
你可以试一下,如果我写错了的话,你可以改掉。
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