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This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求,在FPGA上搭建Cortex-M3软核、图像协处理器,并通过OV5640摄像头采集车牌图像,实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核,依据AHB-Lite总线协议,将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端,设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据(对应20张车牌)存储在RAM中,输出至AHB总线,由Cortex-M3调用并显示识别结果。
Numerical simulation tool for propagating the scalar electric field in optically guiding structures
Electronic-organ---based-on-51-MCU
"Huawei Cup" 17th China Post-Graduate Mathematical Contest in Modeling
The design of intelligent tracking the car based on single chip microcomputer 89 c51 controller.
Object Detection About Masking For Xilinx Summer School
本项目基于GLFW库,读取obj文件中图形的三维信息并显示,同时设置了调整视角以及相机位置的功能
The project loads stl and obj files based on qt, and displays its three-dimensional graphics through QtOpengl
先进PID控制MATLAB仿真 (4th) MATLAB PID算法 仿真 学习
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Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
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