Related Issues (20)
- Missing Verilog component: altsource_probe_component HOT 1
- No "stratum+tcp" support? HOT 4
- Hash rate is 0.02 MH/s HOT 2
- Need help on where to start
- Issue with program-fpga-board.bat HOT 5
- Localization/Translation
- help
- Unable to communicate with FPGA firmware on new device port HOT 14
- Help editing for a papilio duo
- IDX is not defined(sha256_transform) HOT 5
- Is there possibilitiy to run this on our lattice board? HOT 2
- Am I really mining? HOT 15
- Help: Intel Cyclone 10 LP
- cyclone 10 kit support
- Image for Intel CV SoC
- Compare simulation with golden hash values
- FPGA Miner Project update and how to run it on a board(xilinx ZCU102 Development board) that is not in the tested projects directory HOT 9
- [email protected]
- ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable HOT 1
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