pifry / rbc

register based communication generator

Hi there 👋

rbc's Issues

No_expose parameter

Add no_expose parameter that causes field to not be exposed at the entity interface.

Add VHDL tests

• make test harness for generated component, connecting it to avalon agent and clock source
• make test bench

repair bit ranges in documentation

[8:0] when vector is 8 bit length

Add activation bit support in vhdl

add auto resetting bits

Add anothoer bus types to vhdl output

• wishbone
• axi

Refactor vhdl output

Functionality should be separated from bit descriptions. One possible way to do this is to declare bits as constants.

Make entity name from filename

Add method to describe bits combinations in documentation

The goal is to have bits combinations doc in pretty format like

• MUX[1:0] - mux selection.
  • 00 - mode 0,
  • 01 - mode 1,
  • 10 - mode 2
  • 11 - Reserved

Add argparse

Add python tests

Checking output files for existance of certain features.

Make package from it

Add documentation parameters

There should be possible to define documentation only parameters in protocol yaml e.g.

doc:
   title: some title
   footer: footer text
   header: header text
   revision: git

Add default value functionality

Add protocol preprocessing

Protocol should be checked against formal errors (like warning in case different bit widths).

add read request output

When readed data need to be prepared

Make raw md file readable

Add register address to markdown output