Name: Paras Sanjay Gidd
Type: User
Company: VLSI System Design
Bio: A nerd who's trying to learn depths of VLSI to understand & fulfill the needs of industry & be a part of golden era of Electronics.
Location: Manipal University
Blog: https://www.linkedin.com/in/parasgidd/
Paras Sanjay Gidd's Projects
This repository will maintain simulation files and other relevant files on the Bandgap Reference IP worked on in the EICT IITG - VSD Summer Online Internship 2020
This repository contains the design and simulation process and results of potentiometric digital to analog converter.
This repository contains a detailed description of a 10-bit potentiometric digital-to-analog converter. This work is carried out as a part of VSD Research Internship. The repository consists of all files required to design the PDAC. The pre-layout and post-layout simulations have also been provided with DNL and INL calculations.
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
Analog IP of On-chip clock multiplier (PLL) using the OSU 180nm technology
Brightness Controller
Implementation of Power Gating technique in comparator for Low-power applications.
This rep contains standard cells designed on Google sky130 pdk.