Comments (8)
我注意到riscv64-unknown-linux-gnu-gcc是10.2.0,而riscv64-unknown-elf-gcc是12.2.0。前者的编译参数是--with-arch=rv64imafdc,后者则是--with-arch=rv64gc。不确定这是否会有影响?
from xiangshan-doc.
重新用WSL平台编译了riscv-gnu-toolchain,两种工具链的配置如下:
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-linux# riscv64-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=riscv64-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/home/bwoah/my-riscv-newlib/libexec/gcc/riscv64-unknown-elf/12.2.0/lto-wrapper
Target: riscv64-unknown-elf
Configured with: /home/bwoah/XiangShan/riscv-gnu-toolchain/build/../gcc/configure --target=riscv64-unknown-elf --prefix=/home/bwoah/my-riscv-newlib --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g2ee5e430018 --with-system-zlib --enable-tls --with-newlib --with-sysroot=/home/bwoah/my-riscv-newlib/riscv64-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../gcc --disable-multilib --with-abi=lp64d --with-arch=rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-Os -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medlow'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 12.2.0 (g2ee5e430018)
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-linux# riscv64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/bwoah/my-riscv-linux/libexec/gcc/riscv64-unknown-linux-gnu/12.2.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/bwoah/XiangShan/riscv-gnu-toolchain/build/../gcc/configure --target=riscv64-unknown-linux-gnu --prefix=/home/bwoah/my-riscv-linux --with-sysroot=/home/bwoah/my-riscv-linux/sysroot --with-pkgversion=g2ee5e430018 --with-system-zlib --enable-shared --enable-tls --enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap --src=../../gcc --disable-multilib --with-abi=lp64d --with-arch=rv64imafdc_zicsr_zifencei_zba_zbb_zbc_zbs --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2 -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2 -mcmodel=medlow'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 12.2.0 (g2ee5e430018)
在riscv-pk目录下make -j得到如下结果:
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-pk# make clean
rm -rf build
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-pk# make -j 8
RISCV_ROOTFS_HOME=/home/bwoah/XiangShan/riscv-rootfs make -C /home/bwoah/XiangShan/riscv-rootfs
mkdir -p build
mkdir -p build
make[1]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs'
dtc -O dtb -I dts -o build/system.dtb dts/system.dts
cd build && /home/bwoah/XiangShan/riscv-pk/configure --host=riscv64-unknown-elf --with-payload=/home/bwoah/XiangShan/riscv-linux/vmlinux --with-arch=rv64imac --enable-logo
dts/platform.dtsi:19.16-22.7: Warning (unit_address_vs_reg): /soc/mmc: node has a reg or ranges property, but no unit name
dts/platform.dtsi:5.21-11.5: Warning (simple_bus_reg): /soc/clint@2000000: simple-bus unit address format error, expected "38000000"
dts/platform.dtsi:12.24-18.5: Warning (simple_bus_reg): /soc/serial@60000000: simple-bus unit address format error, expected "40600000"
dts/platform.dtsi:19.16-22.7: Warning (simple_bus_reg): /soc/mmc: simple-bus unit address format error, expected "40002000"
dts/platform.dtsi:12.24-18.5: Warning (interrupts_property): /soc/serial@60000000: Missing interrupt-parent
make -s -C apps/hello install
dts/system.dts:34.29-38.6: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
make -s -C apps/stream install
make -s -C apps/busybox install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/hello'
make -s -C apps/redis install
make -s -C apps/dwarf/md5 install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/stream'
make -s -C apps/dwarf/sort install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/busybox'
make -s -C apps/dwarf/wordcount install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/redis'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/md5'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/sort'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/wordcount'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/busybox'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/redis'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/hello'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/stream'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/md5'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/sort'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/wordcount'
make[1]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs'
RISCV_ROOTFS_HOME=/home/bwoah/XiangShan/riscv-rootfs make -C /home/bwoah/XiangShan/riscv-linux CROSS_COMPILE=riscv64-unknown-linux-gnu- ARCH=riscv vmlinux
make[1]: Entering directory '/home/bwoah/XiangShan/riscv-linux'
checking build system type... x86_64-pc-linux-gnu
checking host system type... riscv64-unknown-elf
checking for riscv64-unknown-elf-gcc... riscv64-unknown-elf-gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... yes
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether riscv64-unknown-elf-gcc accepts -g... yes
checking for riscv64-unknown-elf-gcc option to accept ISO C89... none needed
checking for riscv64-unknown-elf-g++... riscv64-unknown-elf-g++
checking whether we are using the GNU C++ compiler... yes
checking whether riscv64-unknown-elf-g++ accepts -g... yes
checking for riscv64-unknown-elf-ar... riscv64-unknown-elf-ar
checking for riscv64-unknown-elf-ranlib... riscv64-unknown-elf-ranlib
checking for riscv64-unknown-elf-readelf... riscv64-unknown-elf-readelf
checking for riscv64-unknown-elf-objcopy... riscv64-unknown-elf-objcopy
checking for a BSD-compatible install... /usr/bin/install -c
checking how to run the C preprocessor... riscv64-unknown-elf-gcc -E
checking for grep that handles long lines and -e... /usr/bin/grep
checking for egrep... /usr/bin/grep -E
checking for ANSI C header files... yes
configure: configuring default subproject : pk
configure: configuring default subproject : bbl
configure: configuring default subproject : softfloat
configure: configuring default subproject : dummy_payload
configure: configuring default subproject : machine
configure: configuring default subproject : util
configure: creating ./config.status
config.status: creating pk.mk
config.status: creating bbl.mk
config.status: creating softfloat.mk
config.status: creating dummy_payload.mk
config.status: creating machine.mk
config.status: creating util.mk
config.status: creating Makefile
config.status: creating config.h
CALL scripts/checksyscalls.sh
:1335:2: warning: #warning syscall rseq not implemented [-Wcpp]
CC init/main.o
CHK include/generated/compile.h
AS arch/riscv/kernel/vdso/flush_icache.o
CC arch/riscv/kernel/process.o
CC arch/riscv/kernel/signal.o
CC arch/riscv/kernel/sys_riscv.o
CC arch/riscv/kernel/traps.o
arch/riscv/kernel/vdso/flush_icache.S: Assembler messages:
arch/riscv/kernel/vdso/flush_icache.S:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[3]: *** [scripts/Makefile.build:417: arch/riscv/kernel/vdso/flush_icache.o] Error 1
make[2]: *** [scripts/Makefile.build:558: arch/riscv/kernel/vdso] Error 2
make[2]: *** Waiting for unfinished jobs....
CC arch/riscv/mm/fault.o
CC arch/riscv/mm/cacheflush.o
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: init/main.o] Error 1
make[1]: *** [Makefile:1029: init] Error 2
make[1]: *** Waiting for unfinished jobs....
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/process.o] Error 1
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
arch/riscv/kernel/traps.c:162: Error: unrecognized opcode csrw sscratch,0', extension
zicsr' required
arch/riscv/kernel/traps.c:164: Error: unrecognized opcode csrw stvec,a5', extension
zicsr' required
arch/riscv/kernel/traps.c:166: Error: unrecognized opcode csrw sie,a5', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/traps.o] Error 1
./arch/riscv/include/asm/cacheflush.h: Assembler messages:
./arch/riscv/include/asm/cacheflush.h:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/sys_riscv.o] Error 1
./arch/riscv/include/asm/cacheflush.h: Assembler messages:
./arch/riscv/include/asm/cacheflush.h:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/mm/cacheflush.o] Error 1
make[2]: *** Waiting for unfinished jobs....
arch/riscv/mm/fault.c: In function 'do_page_fault':
arch/riscv/mm/fault.c:40:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
40 | struct task_struct *tsk;
| ^~~~~~
arch/riscv/kernel/signal.c: Assembler messages:
arch/riscv/kernel/signal.c:175: Error: unrecognized opcode csrs sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:175: Error: unrecognized opcode csrc sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:176: Error: unrecognized opcode csrs sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:176: Error: unrecognized opcode csrc sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:134: Error: unrecognized opcode csrs sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:134: Error: unrecognized opcode csrc sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:73: Error: unrecognized opcode csrs sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:73: Error: unrecognized opcode csrc sstatus,a2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/signal.o] Error 1
make[1]: *** [Makefile:1029: arch/riscv/kernel] Error 2
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
arch/riscv/mm/fault.c:249: Error: unrecognized opcode csrr a2,sptbr', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/mm/fault.o] Error 1
make[1]: *** [Makefile:1029: arch/riscv/mm] Error 2
make[1]: Leaving directory '/home/bwoah/XiangShan/riscv-linux'
make: *** [Makefile:90: /home/bwoah/XiangShan/riscv-linux/vmlinux] Error 2
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-pk# cd ../riscv-linux
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-linux# make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- emu_defconfig
configuration written to .config
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-linux# make ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- emu_de
fconfig
configuration written to .config
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-linux# cd ../riscv-pk
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-pk# make clean
rm -rf build
root@ROG-Zephyrus-G15:/home/bwoah/XiangShan/riscv-pk# make -j
RISCV_ROOTFS_HOME=/home/bwoah/XiangShan/riscv-rootfs make -C /home/bwoah/XiangShan/riscv-rootfs
mkdir -p build
mkdir -p build
make[1]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs'
dtc -O dtb -I dts -o build/system.dtb dts/system.dts
cd build && /home/bwoah/XiangShan/riscv-pk/configure --host=riscv64-unknown-elf --with-payload=/home/bwoah/XiangShan/riscv-linux/vmlinux --with-arch=rv64imac --enable-logo
dts/platform.dtsi:19.16-22.7: Warning (unit_address_vs_reg): /soc/mmc: node has a reg or ranges property, but no unit name
dts/platform.dtsi:5.21-11.5: Warning (simple_bus_reg): /soc/clint@2000000: simple-bus unit address format error, expected "38000000"
dts/platform.dtsi:12.24-18.5: Warning (simple_bus_reg): /soc/serial@60000000: simple-bus unit address format error, expected "40600000"
dts/platform.dtsi:19.16-22.7: Warning (simple_bus_reg): /soc/mmc: simple-bus unit address format error, expected "40002000"
dts/platform.dtsi:12.24-18.5: Warning (interrupts_property): /soc/serial@60000000: Missing interrupt-parent
dts/system.dts:34.29-38.6: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
make -s -C apps/hello install
make -s -C apps/stream install
make -s -C apps/busybox install
make -s -C apps/redis install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/hello'
make -s -C apps/dwarf/md5 install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/stream'
make -s -C apps/dwarf/sort install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/busybox'
make -s -C apps/dwarf/wordcount install
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/redis'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/md5'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/wordcount'
make[2]: Entering directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/sort'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/redis'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/busybox'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/hello'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/stream'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/wordcount'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/md5'
make[2]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs/apps/dwarf/sort'
make[1]: Leaving directory '/home/bwoah/XiangShan/riscv-rootfs'
RISCV_ROOTFS_HOME=/home/bwoah/XiangShan/riscv-rootfs make -C /home/bwoah/XiangShan/riscv-linux CROSS_COMPILE=riscv64-unknown-linux-gnu- ARCH=riscv vmlinux
make[1]: Entering directory '/home/bwoah/XiangShan/riscv-linux'
checking build system type... x86_64-pc-linux-gnu
checking host system type... riscv64-unknown-elf
checking for riscv64-unknown-elf-gcc... riscv64-unknown-elf-gcc
checking whether the C compiler works... yes
checking for C compiler default output file name... a.out
checking for suffix of executables...
checking whether we are cross compiling... yes
checking for suffix of object files... o
checking whether we are using the GNU C compiler... yes
checking whether riscv64-unknown-elf-gcc accepts -g... yes
checking for riscv64-unknown-elf-gcc option to accept ISO C89... none needed
checking for riscv64-unknown-elf-g++... riscv64-unknown-elf-g++
checking whether we are using the GNU C++ compiler... yes
checking whether riscv64-unknown-elf-g++ accepts -g... yes
checking for riscv64-unknown-elf-ar... riscv64-unknown-elf-ar
checking for riscv64-unknown-elf-ranlib... riscv64-unknown-elf-ranlib
checking for riscv64-unknown-elf-readelf... riscv64-unknown-elf-readelf
checking for riscv64-unknown-elf-objcopy... riscv64-unknown-elf-objcopy
checking for a BSD-compatible install... /usr/bin/install -c
checking how to run the C preprocessor... riscv64-unknown-elf-gcc -E
checking for grep that handles long lines and -e... /usr/bin/grep
checking for egrep... /usr/bin/grep -E
checking for ANSI C header files... yes
configure: configuring default subproject : pk
configure: configuring default subproject : bbl
configure: configuring default subproject : softfloat
configure: configuring default subproject : dummy_payload
configure: configuring default subproject : machine
configure: configuring default subproject : util
configure: creating ./config.status
config.status: creating pk.mk
config.status: creating bbl.mk
config.status: creating softfloat.mk
config.status: creating dummy_payload.mk
config.status: creating machine.mk
config.status: creating util.mk
config.status: creating Makefile
config.status: creating config.h
scripts/kconfig/conf --syncconfig Kconfig
CALL scripts/checksyscalls.sh
:1335:2: warning: #warning syscall rseq not implemented [-Wcpp]
CC init/main.o
CHK include/generated/compile.h
AS arch/riscv/kernel/vdso/flush_icache.o
CC arch/riscv/kernel/process.o
CC arch/riscv/kernel/signal.o
CC arch/riscv/kernel/traps.o
CC arch/riscv/kernel/sys_riscv.o
arch/riscv/kernel/vdso/flush_icache.S: Assembler messages:
arch/riscv/kernel/vdso/flush_icache.S:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[3]: *** [scripts/Makefile.build:417: arch/riscv/kernel/vdso/flush_icache.o] Error 1
make[2]: *** [scripts/Makefile.build:558: arch/riscv/kernel/vdso] Error 2
make[2]: *** Waiting for unfinished jobs....
CC arch/riscv/mm/fault.o
CC arch/riscv/mm/cacheflush.o
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:24: Error: unrecognized opcode csrr a5,sstatus', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: init/main.o] Error 1
make[1]: *** [Makefile:1029: init] Error 2
make[1]: *** Waiting for unfinished jobs....
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/process.o] Error 1
./arch/riscv/include/asm/cacheflush.h: Assembler messages:
./arch/riscv/include/asm/cacheflush.h:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/sys_riscv.o] Error 1
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:36: Error: unrecognized opcode csrc sstatus,2', extension
zicsr' required
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
arch/riscv/kernel/traps.c:162: Error: unrecognized opcode csrw sscratch,0', extension
zicsr' required
arch/riscv/kernel/traps.c:164: Error: unrecognized opcode csrw stvec,a5', extension
zicsr' required
arch/riscv/kernel/traps.c:166: Error: unrecognized opcode csrw sie,a5', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/traps.o] Error 1
arch/riscv/kernel/signal.c: Assembler messages:
arch/riscv/kernel/signal.c:175: Error: unrecognized opcode csrs sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:175: Error: unrecognized opcode csrc sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:176: Error: unrecognized opcode csrs sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:176: Error: unrecognized opcode csrc sstatus,a3', extension
zicsr' required
arch/riscv/kernel/signal.c:134: Error: unrecognized opcode csrs sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:134: Error: unrecognized opcode csrc sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:73: Error: unrecognized opcode csrs sstatus,a2', extension
zicsr' required
arch/riscv/kernel/signal.c:73: Error: unrecognized opcode csrc sstatus,a2', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/kernel/signal.o] Error 1
make[1]: *** [Makefile:1029: arch/riscv/kernel] Error 2
./arch/riscv/include/asm/cacheflush.h: Assembler messages:
./arch/riscv/include/asm/cacheflush.h:25: Error: unrecognized opcode fence.i', extension
zifencei' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/mm/cacheflush.o] Error 1
make[2]: *** Waiting for unfinished jobs....
arch/riscv/mm/fault.c: In function 'do_page_fault':
arch/riscv/mm/fault.c:40:9: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
40 | struct task_struct *tsk;
| ^~~~~~
./arch/riscv/include/asm/irqflags.h: Assembler messages:
./arch/riscv/include/asm/irqflags.h:30: Error: unrecognized opcode csrs sstatus,2', extension
zicsr' required
arch/riscv/mm/fault.c:249: Error: unrecognized opcode csrr a2,sptbr', extension
zicsr' required
make[2]: *** [scripts/Makefile.build:317: arch/riscv/mm/fault.o] Error 1
make[1]: *** [Makefile:1029: arch/riscv/mm] Error 2
make[1]: Leaving directory '/home/bwoah/XiangShan/riscv-linux'
make: *** [Makefile:90: /home/bwoah/XiangShan/riscv-linux/vmlinux] Error 2
上述两个扩展指令集应该已经被涵盖,为何会有报错?
恳求解答!
from xiangshan-doc.
看起来是as出错,你可以贴一下AS的信息(比如路径、 版本)
from xiangshan-doc.
root@ROG-Zephyrus-G15:~# as --version
Copyright (C) 2022 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `x86_64-linux-gnu'.
root@ROG-Zephyrus-G15:~# riscv64-unknown-linux-gnu-as --version
GNU assembler (GNU Binutils) 2.40.0.20230214
Copyright (C) 2023 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `riscv64-unknown-linux-gnu'.
root@ROG-Zephyrus-G15:/home/bwoah/my-riscv-linux/bin# ls
riscv64-unknown-linux-gnu-addr2line riscv64-unknown-linux-gnu-gcc-nm riscv64-unknown-linux-gnu-lto-dump
riscv64-unknown-linux-gnu-ar riscv64-unknown-linux-gnu-gcc-ranlib riscv64-unknown-linux-gnu-nm
riscv64-unknown-linux-gnu-as riscv64-unknown-linux-gnu-gcov riscv64-unknown-linux-gnu-objcopy
riscv64-unknown-linux-gnu-c++ riscv64-unknown-linux-gnu-gcov-dump riscv64-unknown-linux-gnu-objdump
riscv64-unknown-linux-gnu-c++filt riscv64-unknown-linux-gnu-gcov-tool riscv64-unknown-linux-gnu-ranlib
riscv64-unknown-linux-gnu-cpp riscv64-unknown-linux-gnu-gdb riscv64-unknown-linux-gnu-readelf
riscv64-unknown-linux-gnu-elfedit riscv64-unknown-linux-gnu-gdb-add-index riscv64-unknown-linux-gnu-run
riscv64-unknown-linux-gnu-g++ riscv64-unknown-linux-gnu-gfortran riscv64-unknown-linux-gnu-size
riscv64-unknown-linux-gnu-gcc riscv64-unknown-linux-gnu-gprof riscv64-unknown-linux-gnu-strings
riscv64-unknown-linux-gnu-gcc-12.2.0 riscv64-unknown-linux-gnu-ld riscv64-unknown-linux-gnu-strip
riscv64-unknown-linux-gnu-gcc-ar riscv64-unknown-linux-gnu-ld.bfd
from xiangshan-doc.
根据Reddit讨论,近期的GCC工具链默认没有包括Zicsr支持,上文gcc版本为12,应当受到了该问题影响,可以参考讨论中给出的解决方法尝试下。我们开发时通常使用gcc 10,不受该更改影响,应该是之前没有发现该问题的原因。
from xiangshan-doc.
根据Reddit讨论,近期的GCC工具链默认没有包括Zicsr支持,上文gcc版本为12,应当受到了该问题影响,可以参考讨论中给出的解决方法尝试下。我们开发时通常使用gcc 10,不受该更改影响,应该是之前没有发现该问题的原因。
感谢回复,我看到这个issue里有提到类似的问题,但是我的toolchain应该是清晰指明了ziscr和zifencei的,理论上不会出现这样的问题?
from xiangshan-doc.
实际编译用的march是编译时命令行传进去的,不是工具链编译时候完全确定的。工具链编译时候的march只影响lib和默认的march
如果要使用香山的环境,切换到gcc 10.2.0
如果要用新版工具链,需要在编译环境中march加入zicsr,参考OpenXiangShan/riscv-pk@8927a5f30e0e11db81f4dc2a1d24b796360501ef对riscv-pk编译选项的改动
from xiangshan-doc.
目前问题得到解决,工具链编译时需指明ziscr zifencei,此外riscv-pk的Makefile中需要将BBL_CONFIG中--with-arch选项增加_ziscr_zifencei,可以成功编译。
from xiangshan-doc.
Related Issues (20)
- checkpoint的生成 HOT 27
- riscv-rootfs使用新的app后运行报错Failed to execute /init (error -8) HOT 1
- 香山处理器结构图,打不开啊 HOT 1
- tutorial\香山Tutorial.pdf,P20 香山Tutorial 讨论群 二维码已经过期,请及时更新 HOT 1
- 关于Minjie 论文的疑问 HOT 3
- 香山性能瓶颈分析PPT参考文献 HOT 1
- 请求间接转移指令预测相关数据
- 对于 Cache别名问题 章节表述的一些疑问 HOT 1
- checkpointing运行后,文件夹为空,加了dont-skip-boot以后,checkpoint遇到crash HOT 3
- 2023 年的RISC-V峰会都结束了,资料可以更新到 2023 啦 HOT 2
- 仿真环境下,香山核运行Linux镜像遇到无法引导的错误 HOT 11
- 三篇Difftest文章链接无法访问 HOT 1
- The description of VCS Simulation +dump-wave arg is out of date
- spec_gen.py 中的spec_common文件夹 HOT 4
- 生成的simpoint_bbv.gz文件是空 HOT 21
- 内存16GB生成simpoint的时候bootload挂住 HOT 1
- DRAMSIM3 文档 HOT 1
- riscv-pk打包bbl后启动时所有动态链接库均无法找到 HOT 13
- 编译链接kernel的BBL时报错
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from xiangshan-doc.