nykwon000 Goto Github PK

beginner-physical-design

This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.

breaking_cycles_in_noisy_hierarchies

breaking cycles in noisy hierarchies

cadence_power_switches

cadence flow for genus and innovus with UPF added.

cic2015_verilog

CIC競賽 cell-based design組 2015年考古題 simulation tool : NCVerilog synthesis tool : Design Compiler

cpu-internals

Intel / AMD CPU Internals

dag

digital-flow

This is a tutorial on standard digital design flow

fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

graywolf

hyper-v-internals

Internals information about Hyper-V

hyper-v-scripts

Hyper-V scripts

hyperdeceit

HyperDeceit is the ultimate all-in-one library that emulates Hyper-V for Windows, giving you the ability to intercept and manipulate operating system tasks with ease.

i2c

I2C controller core

iitp

linux-binary

리눅스 바이너리 분석

linux-kernel

리눅스 커널

microv

A micro hypervisor for running micro VMs

mint64os-examples

"64비트 멀티코어 OS 원리와 구조" 의 예제 소스 코드

mips_16

Educational 16-bit MIPS Processor

ncsim

Stuff for a lecture at Heidelberg University I'm attending

nykwon000.github.io

opensourcephydesign

SOC Physical Design Workshop with Open Source Tools

pdk_onc5

Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

plsi

Palmer's VLSI scripts

qemu_analysis

My Slide

qemu_blog

A series of posts about QEMU internals:

raspberry-pi-os

Learning operating system development using Linux kernel and Raspberry Pi

raspi3-tutorial

Bare metal Raspberry Pi 3 tutorials

riscv-hyp-tests

A bare-metal application to test specific features of the risc-v hypervisor extension