Comments (6)
+1, I would really appreciate it because I cannot get this to work whatever I try.
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I've been reading cutlass doc and source code for couple of weeks, but still don't get it. I'm thinking it probably because 1) too many use of compilation time concept 2) there are many "shape"s, which might not be easily understood without pictures.
So my suggestion is will you please add more figures to help people to understand the concept and your design?
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CUTLASS is a header library. Essentially just need to include all the header files and compile with one nvcc line
nvcc -Ipath_to_/cutlass/include -Ipath_to_/cutlass/examples/common -Ipath_to/build/include -Ipath_to/cutlass/tools/util/include -isystem=path_to/cuda/include -O3 -DNDEBUG -Xcompiler=-fPIE -DCUTLASS_ENABLE_TENSOR_CORE_MMA=1 -Xcompiler=-Wconversion -Xcompiler=-fno-strict-aliasing -gencode=arch=compute_75,code=[sm_75,compute_75] -std=c++11 -x cu -c path_to_cu -o path_to_binary
You can try below command to see an example
make 08_turing_tensorop_gemm VERBOSE=1
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@Peter9606 , below two GTC talks should be helpful
https://developer.nvidia.com/gtc/2020/video/s21745-vid
https://on-demand.gputechconf.com/gtc/2018/presentation/s8854-cutlass-software-primitives-for-dense-linear-algebra-at-all-levels-and-scales-within-cuda.pdf
Most of the complication comes from address calculation. Dumping the load/store addresses from the device can help you understand.
examples/03_visualize_layout is also a tool help you visualize the layout for you.
If you could let me know your goal (such as tensor core or not, sm number, data type, mainloop or epilogue, etc.), I can give you more specific help.
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@hwu36 The slides from GTC2020 really helps. Thank you!
Actually I'm thinking of leveraging cutlass to efficiently move memory between GMEM, SMEM and registers and accelerate computing on CUDA cores regards to deep learning, because cutlass is decomposable. Sure, I'll pop up specific question.
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the link i send out includes 2020 video and 2018 slides.
2018 slides talk more about the overview of the gemm computation in cuda. 2020 video focuses more on tensor core computations.
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Related Issues (20)
- [BUG] Error Internal with large batch size in gemm::device::GemmBatched HOT 3
- [QST] how can i do w4a8 (int4 * int8) using cutlass? HOT 6
- [QST] Checking Tensor Shape returns 0 HOT 4
- [BUG] Build failed with nvcc "-G" on H100 HOT 8
- [cute gemm] HOT 2
- [QST] Constraint of Tensor Layout in FP8 GEMM Kernel HOT 4
- [QST] Build hangs on AWS p3.2xlarge Ubuntu HOT 7
- [QST] Epilogue Swizzle HOT 3
- [QST] Confusing stride definition in example_57
- [QST] Understanding `retile_*` HOT 4
- [BUG] Failure in TensorRef.rank2_column_major_interleaved test with Intel LLVM compiler HOT 3
- [QST] `uint4b / int4` Mixed Type GEMM using `Cutlass 3.x` for `Ampere`
- [QST] TiledMMA with `>1` Atoms in K dimension --- how to reduce? HOT 4
- [QST] What does partition_S and partition_fragment_A do? And what does tQgQ and tSrQ denote? HOT 7
- [QST] HOT 2
- [QST] Unsigned INT8 GEMM HOT 4
- [QST] WGMMA swizzle layout HOT 5
- [QST] Tile is not evenly divisible HOT 14
- [QST] Does GEMM support vectors of alpha and beta? HOT 4
- [QST] `uint4/int4` Mixed Type Tensorcore MMA using `Cutlass 3.x / CuTe` HOT 3
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